Problems with Phase Shifter Simulation code

[OvErFlO]

Phase Shifter Simulation

I have write this code to use 2 signals with a 90° fase shifter...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity clock_phase is
    Port ( clk_in : in std_logic;
           clk_x2 : out std_logic;
           clk_0 : out std_logic;
           clk_90 : out std_logic);
end clock_phase;

architecture Behavioral of clock_phase is

   component IBUFG
         port (I: in std_logic; O: out std_logic);
   end component;

	signal clk_in1,net1,net2,net3,net4 : std_logic := '0';
begin

   U1:  IBUFG port map (I => clk_in, O => clk_in1);
	
	div_clock : process (clk_in1)
	begin
		
		if (rising_edge (clk_in1)) then
				
					net1<= not net1;
				
		end if;

	end process div_clock;
	
	div_clock2 : process (clk_in1)
	begin

		if (falling_edge (clk_in1)) then
				
					net2<= not net2;
				
		end if;

	end process div_clock2;
	
	clk_0 <= net1;
	clk_90 <= net2;
	clk_x2 <= clk_in1;

end Behavioral;

There's a clock of 500Khz

When I try to do a Logical Simulation with ModelSim it's works

**broken link removed**

If I try to do a Place&Route Simulation clk_90 is 'X'

**broken link removed**

But when I use Active HDL in both case I have a good results.. Why ?


Thanks