problems with Lattice ispLEVER, possibly Synplify synthesis

[Elephantus]

isplever problem process and signal

Hi all. I am trying to build a design for lattice ECP2 fpga and the ispLEVER map returns the following error:

"This device does not allow routing COUT signal of RIPPLE comp
using regular routing resources. Signal
'u_ctrl/brst_x_1_cry_12' of comp
'u_ctrl/brst_x_1_cry_11_0' must drive
CIN of RIPPLE and use fast carry. Please check your design."

Now, the only place in the code where brst_x is assigned, is this:

   process (gsr, clk)
   begin
      if (gsr = '1') then
         brst_x <= (others => '0');
      elsif (rising_edge(clk)) then
         brst_x<= brst - x;
      end if;
   end process;

The error would suggest that something is wrong in the synthesis of the subtract operation. One thing is, brst_x and brst are 32 bit values, x is a 13 bit value - however this synthesized well using xilinx xst. Has anyone experienced problems such as these?

I would appreciate any help.