Hey there,
It is very common to have "x" during full timing SDF simulation. If your simulation is with postlayout netlist, and +notimingchecks and +delay_mode_zero You need to worried really,, but very little.
Most of the PnR tools will change/optimize the logic in such as way that it will work in actual silicon, but can not simulated because of the uninitialized registers. So check your PnR tool, and look for any bug history about optmization.
-Milind Sonawane