problems about verification~

[jojo12520]

hi,all

can u tell me the IC hardware design flow?
dose verification include function verification, timing verification, fomality verification and DRC/LVS verification?
what's the order and purpose of the verifications?

thanks!

 

[jiang]

The main flow is function verification -> timing verification after synthesizing -> formality verification -> DRC/LVS after P&R.

function verification => of course, you have to make sure the function is OK.
timing verification => to check gate level netlist timing is matching the spec
fomality verification => to make sure the functionality of gate level is the same with RTL code, because tools maybe modify the netlist or by ECO
DRC/LVS => to check P&R tool result

 

[dechen]

gate level simulation