This means, the clock to the capture flop (C2) can be ahead of clk to the launch flop (c1) by 5.7ns.
So the delay can be of any value ranging from -5.7 to some positive value to meet the setup time.
Hold check:
U1 + holdtime(c2) <= Tcq(c1) + Tcomb(min);
U1 + 0.5 <= 0.5 + 0.5 + 0.5 + 0.5
U1 <= 1.5ns
Therefore to meet both the setup and hold time, -5.7ns <= U1 <= 1.5ns