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problems about setup time and hold time

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hfooo1

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U1 is a cell with certain delay.
now suppose the value of delay is variational.

Q1: what is the range of the delay value which meet the setup time of C2?
Q2: what is the range of the delay value which meet the hold time of C2?

thank u
 

hfooo1

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o
may someone share his opinion
 

kvingle

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you have not commented anything on delay added by U1 buffer
( sorry but i cant read japanise or chinise ....or whatsoever it is..)

the simple way to calulate the minimum delay (maximum frequency)is

C1(clock to out)+ maximum combination delay by logic 1+logic2 + logic3 + setup time of C2.

i.e.
=0.5+1+1+1+0.8
=4.3
 

useless_skew

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hfooo1 said:
U1 is a cell with certain delay.
now suppose the value of delay is variational.

Q1: what is the range of the delay value which meet the setup time of C2?
Q2: what is the range of the delay value which meet the hold time of C2?

thank u
Setup check:
Tclk = 10ns;
Setup time = 0.8ns;

Tclk - 0.8ns + U1 >= Tcq + Tcomb(max)

10 - 0.8 + U1 >= 0.5 + 1 + 1 + 1
 

useless_skew

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Therefore, U1 >= -9.2 + 3.5

U1 >= -5.7ns

This means, the clock to the capture flop (C2) can be ahead of clk to the launch flop (c1) by 5.7ns.
So the delay can be of any value ranging from -5.7 to some positive value to meet the setup time.

Hold check:

U1 + holdtime(c2) <= Tcq(c1) + Tcomb(min);

U1 + 0.5 <= 0.5 + 0.5 + 0.5 + 0.5

U1 <= 1.5ns


Therefore to meet both the setup and hold time, -5.7ns <= U1 <= 1.5ns
 

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