Problem with Xilinx DDR2 core while implementation

[satyakumar]

xilinx ddr2 core

I synthesized with syplify 8.8 then implemented with xilinx10.1i it works fine, but when I synthesized with synplify 9.4 and if I implement with 10.1i I get the fallowing map error.
***************************************************************
ERRORack:679 - Unable to obey design constraints
(MACRONAME=One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_
mem_if_top_0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/One_DDR2_INST.bank1_cn
trl_inst$comp1.DDR2.DDR2_Con.u_ddr2_top_0.u_mem_if_top_0.u_phy_top_0.u_phy_io
_0$gen_dq\.10\.u_iob_dq$stg2_capture, RLOC=X0Y0) which require the
combination of the following symbols into a single SLICE component:
FLOP symbol
"One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top
_0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/gen_stg2_2m.u_ff_stg2a_fall"
(Output Signal =
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/stg2a_out_fall)
FLOP symbol
"One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top
_0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/gen_stg2_2m.u_ff_stg3b_fall"
(Output Signal =
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/stg3b_out_fall)
FLOP symbol
"One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top
_0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/gen_stg2_2m.u_ff_stg2a_rise"
(Output Signal =
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/stg2a_out_rise_0)
FLOP symbol
"One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top
_0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/gen_stg2_2m.u_ff_stg3b_rise"
(Output Signal =
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/stg3b_out_rise_0)
Carry symbol
"One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top
_0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/gen_stg2_2m.u_dummy_carry_stg2a"
(Output Signal =
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/un1_u_dummy_carry_stg2a(0))
The top reasons for failure were:
-> CARRY4
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/gen_stg2_2m.u_dummy_carry_stg2a
can not be packed because the O0 output signal
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/un1_u_dummy_carry_stg2a(0) has a
conflict with the AOUTMUX. The
One_DDR2_INST/bank1_cntrl_inst/comp1/DDR2/DDR2_Con/u_ddr2_top_0/u_mem_if_top_
0/u_phy_top_0/u_phy_io_0/gen_dq.10.u_iob_dq/dummy_carry4_co_a_1(0) signal
already uses the AOUTMUX.
Please correct the design constraints accordingly.
******************************************
can any one provide some fixes for this error

Thanks and regards
Satyakumar

 

[BlackOps]

xilinx ddr2 problems

it says clearly at the end...design constraints problem, check the UCF file and interconnection of the signals

 

[flavenant]

aoutmux

Hi satyakumar,

Have you solved your problem, because I have the same message ?

It is not so easy to check constraints because there are auto-generated in VHDL+UCF by the MIG controlleur generator.

Thanks in advance.