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Problem with Verilog code

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Fdez.CA

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This is a code created for a class based on some equations given by the teacher, but when we put them in Quartus, send us an error and we have no idea why.

Code:
module get100(CLK,X,Y,A,B,C,D,E,F,G);
	input X,Y,CLK;
	output reg A,B,C,D,E,F,G;
	always@ (posedge CLK)
		assign A=((((~A&~B&~C&~D&~E&~F&~G)|(~A&~B&~C&~D&E&F&G))&~X&Y)|(((~A&B&~C&~D&E&~F&~G)|(~A&~B&C&~D&~E&~F&~G))&X&Y));
		assign B=((((A&~B&~C&D&E&~F&~G)|(~A&~B&~C&~D&E&F&G))&~X&Y)|(((~A&~B&~C&D&E&F&G)|(~A&B&~C&~D&~E&~F&~G))&X&Y));
		assign C=(((A&~B&~C&D&E&F&G)&~X&Y)|((~A&~B&~C&~D&E&F&~G)&X&Y));
		assign D=((((~A&~B&~C&~D&~E&~F)|(~A&~B&~C&~D&E&F&~G)|(~A&~C&~D&~E&~F&~G))&~X&Y)|(((~A&~B&~C&~D&~E&~F)|(~A&B&~C&~D&E&~F&~G)|(~A&~B&C&~D&~E&F&~G))&X&Y));
		assign E=((((~A&~B&~C&~D&~E&~F)|(~A&~B&C&~D&~E&F&~G)|(~A&~B&~C&~D&E&F&~G)|(A&~B&~C&D&E&~F&~G)|(~A&~C&~D&~E&~F&~G))&~X&Y)|(((~A&~B&~C&~D&~E&~F)|(~A&B&~C&~D&~F&~G)|(A&~B&~C&D&E&~F&~G)|(~A&~B&C&~D&~E&F&~G))&X&Y));
		assign F=((((~A&~B&~C&~D&~E&~F&G)|(A&~B&~C&D&E&F&G)|(~A&~B&C&~D&~E&F&~G)|(~A&B&~C&~D&~E&~F&~G))&~X&Y)|(((~A&~B&~C&~D&~E&~F&~G)|(A&~B&~C&D&E&~F&~G)|(~A&~B&~C&~D&E&F&~G)|(~A&~B&C&~D&~E&F&~G))&X&Y));
		assign G=((((~A&~B&~C&~D&~E&~F&G)|(~A&B&~C&~D&~E&~F&~G)|(~A&~B&~C&D&E&~F&~G))&~X&Y)|(((~A&~B&~C&~D&~E&~F&~G)|(~A&~B&C&~D&~E&F&~G)|(A&~B&~C&D&E&F&G))&X&Y));
endmodule
The thrown error is:

Error (10219): Verilog HDL Continuous Assignment error at get100.v(6): object "B" on left-hand side of assignment must have a net type
Error (10219): Verilog HDL Continuous Assignment error at get100.v(6): object "C" on left-hand side of assignment must have a net type
Error (10219): Verilog HDL Continuous Assignment error at get100.v(6): object "D" on left-hand side of assignment must have a net type
Error (10219): Verilog HDL Continuous Assignment error at get100.v(6): object "E" on left-hand side of assignment must have a net type
Error (10219): Verilog HDL Continuous Assignment error at get100.v(6): object "F" on left-hand side of assignment must have a net type
Error (10219): Verilog HDL Continuous Assignment error at get100.v(6): object "G" on left-hand side of assignment must have a net type

Anyone know what's wrong? please :cry:
 

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1. Read a Verilog book.
2. Read a Verilog book.
3. Read a Verilog book.


4. Remove the assigns they are for continuous assignments and they are NOT used in an always block.
5. change all your '=' (blocking assignments) in the edge sensitive always block (describing sequential registers) to '<=' (non-blocking assignments).
 

Fdez.CA

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The problem is that my teacher says that the assigns must be used inside the always bl in this homework, someone tell me that the problem is in the parenthesis, but I cheked every parenthesis and nothins seems wrong to me...
 

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then don't use reg on your outputs as assign cannot be applied to a reg variable.

But truthfully I'm not certain you're code will synthesize correctly given you are using an edge sensitive always block and an assign. The "wire" default for the outputs (without the reg) will imply you're trying to create a combinational circuit, but then you have a "clock".

This is why you design a circuit (schematic) then describe that circuit in Verilog, which is why it's referred to as a Hardware Description Language.
 

raghavkmr

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yes assign can be used inside always block, and it can be used with reg

please use begin and end in always block

e.g.
always@ (posedge CLK)
begin

your rest of code

end
endmodule
 

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