Problem with using Samsung DDR model wih Modelsim

[bibo1978]

Have anyone used samsung DDR-model with Modelsim, it seems that I have a problem with it, the DQS signal on the write process goes to X state, I believe that the DDR-model and controller tries to force a value on the DQS, I don't know for sure where is the problem,
however, I am using Modelsim 5.5e PLUS to do the simulation because the controller design is in VHDL.
I had verified the design with the micron model but the micron model doesn't support the tDQSS time parameter so I tried the samsung model.

There is another problem with the samsung model as well:
always a tCKmax violation occurs although my testbench runs at tCK less than tCK max, a tRASmax violation occurs also, although I refresh every 15.6 us so there is no way I will exceed tRAS max.

can anybody help me, I believe that there is a Denali model that can verify a controller with any ddr. can anyone help me to find this model

 

[nand_gates]

tckmax

More details are needed
1. In what mode you are operating the DDR RAM?
2. Can you post the wave forms!

Better you use Denali models! I am using them! both for
samsung and micron rams.

Check whether ur memory models supports any message dumpings
such as write at addr xxxxx data yyyyy
read from addr xxxxx data yyyyy
If yes Turn on memory model messages.
And post the log here!

 

[bibo1978]

micron memory model violations

I am operating in:
1- CAS latency 2.5
2- Burst length 8
3- sequential
, there is a dump messages in samsung ddr model, as I stated the dumped message in the write process:
# 10652.2 ns >> active ( B Bank)
# 10661.4 ns Warning: tCKmax violation
# 10670.7 ns Warning: tCKmax violation --- only 9.8 ns after first violation !!!
# 10680.0 ns Warning: tCKmax violation
# 10689.2 ns Warning: tCKmax violation
# 10698.5 ns Warning: tCKmax violation
# 10698.5 ns >> write ( B Bank )
# 10707.7 ns Warning: tCKmax violation
# 10717.0 ns Warning: tCKmax violation
# 10726.3 ns Warning: tCKmax violation
# 10735.5 ns Warning: tCKmax violation
# 10744.8 ns Warning: tCKmax violation
# 10754.0 ns Warning: tCKmax violation
# 10763.3 ns Warning: tCKmax violation
# 10772.6 ns Warning: tCKmax violation
# 10772.6 ns Warning: tRASmax violation( A Bank )
# 10772.6 ns >> precharge ( all bank )

of course there is no tCKmax violation or tRASmax violation this is a defaux in the model
the read process is the same