[SOLVED] problem with transistor model d flip flop

[diaz080]

friends..i'ma beginner to cadence.. last day i tried to implement pose edge d flip flop using transistors(logic gates). Now i'm facing a problem.The circuit is passing data line on both edge of the clock. Can anybody help me to figure out what went wrong with this circuit design

 

[Audioguru]

I fixed your awful negative image.

 

[diaz080]

any idea? ..

 

[BradtheRad]

Question: Your schematic has NAND gates which have 3 inputs. I wonder what the simulator does about those unused inputs? Are they recognized as high or low?

Likewise, what level are you applying to the D (Data) inputs?

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Falstad's simulator comes with a similar flip-flop. The Nand gates are all 2-input. The scope traces show how it is supposed to function.

 

[diaz080]

3rd input is active low set & reset..i'm applying a pulse to the d line

 

[dick_freebird]

It looks roughly right to me, only the action is on the
negative clock edge. By eye it looks like Ck/ catches
the right state of d into q.

 

[diaz080]

@dick_freebird nope.it is happening in both edges. i think i figured out the problem. Problem was with the sizing of the logic gates which i used . Now it is working correctly. thanks guys

 

[FvM]

Problem was with the sizing of the logic gates which i used . Now it is working correctly.

Yes, looks like the unwanted negative edge action is due to irregular timing, slave stage is deactivated too late.