Problem with Tranmission gate

[rashmiav]

Hello,

I am using a transmission gate to write data onto the bitline of my SRAM.

When both the NMOS and PMOS of my TX gate are off, the Tx gate should not write anything onto my Bitline. But the Tx gate produces some unknown voltage when it is Off which should not be written onto the Bitline.

Could anyone suggest how this problem can be overcome?

 

[D.A.(Tony)Stewart]

If you can isolate the leakage from word Addressing or bit Reading, it would help to define the issue.

Current leakage can exist when dq/dV injects current. I think it is called the butterfly curve.

You might need to explain your topology and geometry and calculated noise margin.

I read that 8T has more immunity than 6T and 10T hysteresis cell type in sub-threshold logic gives the best.

 

[rashmiav]

If you can isolate the leakage from word Addressing or bit Reading, it would help to define the issue.

Current leakage can exist when dq/dV injects current. I think it is called the butterfly curve.

You might need to explain your topology and geometry and calculated noise margin.

I read that 8T has more immunity than 6T and 10T hysteresis cell type in sub-threshold logic gives the best.

I am using 8T Bit cell with 3 bitlines. Could you explain how the high impedance state can be isolated from affecting the Bitlines?

 

[erikl]

... how the high impedance state can be isolated from affecting the Bitlines?

Aren't the bitlines anyway precharged to 1 before reading?
And charged to the required values before writing.

So why should a former high impedance state matter?

 

[rashmiav]

Aren't the bitlines anyway precharged to 1 before reading?
And charged to the required values before writing.

So why should a former high impedance state matter?

My column decoder should choose one of the coulmns of my SRAM based on the address and write only to the bitlines corresponding to that column.

For this, I am using Tx gates whose PMOS and NMOS gate inputs are used to select the column. When the Tx gate is Off, the bitlines connected to that column should remain unaltered. But, since the Tx gate produces random high impedance voltage as the output(which is connected to the bitline directly), I fear if this high impedance value will be written as high or low value in the bitline and alter the actual value on the bitlines(which should not happen ideally).


So is there any way to isolate the bitline when the Tx gate is switched off? Or is there any other solution to this problem?

 

[erikl]

So is there any way to isolate the bitline when the Tx gate is switched off?

Actually the bitline is isolated when the Tx gate is switched off.

The random high impedance voltage at the output presumably is caused by charge injection/capacitive coupling during the switch-off event, probably affected by its previous voltage level.

Or is there any other solution to this problem?

You could nail the bitlines to your preferred voltage level (probably a logic 1) via a - momentary or continuous - high-impedance connection - sort of precharge mechanism.