I will explain my original problem,
I design a differential common gate LNA working at 2GHz with LC tank at output(QL = 10 low which corresponds to higher BW)
In order to account for the loading of the following mixers, I modeled its capacitance with some value.
Then, The loading mixers are 3 mixers, direct conversion Active mixers.
3 mixers due to some specs. in the system design.
To simulate the IIP3 with the mixers, I switch off the clock, i.e. clk = vdd and clk_bar=gnd, such that I get their loading on the LNA stage.
Doing this hurts the LNA linearity so much(from 4dBm to -4dBm).
After some debuging, I saw the balun issue i mentioned previuosly.
How do I measure the IIP3?
by PSS and PAC:
f1 is the PSS freq. and f2 is the PAC freq.
These freq.s are inserted in the input port which is connected to an ideal balun that transform impedance from 50 ohm to 100 ohm differential, i.e. sine wave and pac magnitude with same magnitude prf dBm respectively.
then, in PAC direct plot window, i choose ipn curves and 1st harmonic is f2
and 3rd order harmonic is 2*f2-f1.
and I choose differential nets as output and select the LNA output nets.