problem with similar packages in different libraries

[lablasa]

HI!
I'm working with 2 libraries (proj_A and proj_B, each library has its own package (pkg_A and pkg_B) since each library should be synthetisizable as a "standalone library".
These packages are similar (both declare array types:
type a_2bit is array (natural range <>) of std_logic_vector(1 downto 0);
type a_8bit is array (natural range <>) of std_logic_vector(7 downto 0);
type a_32bit is array (natural range <>) of std_logic_vector(31 downto 0);
and so on...) and I need both.
When I instantiate proj_A in proj_B, I declare pkg_B only:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

LIBRARY proj_B;
USE proj_B.pkg_B.ALL;

LIBRARY proj_A;

entity ent_proj_B is
....
end ent_proj_B;

architecture struct of ent_proj_B is
...
component ent_proj_A
port....
end component;
.....
end struct;

The ports of proj_A are arrays, declared both in pkg_A and pkg_B but modelsim reports
Failure: (vsim-3807) Types do not match between component and entity for port "xxx"

I'm trying to understand if it's just a configuration problem, something concernig with the tools I'm using or, simply, I can't use array types as ports in different libraries...

Thanks,
lablasa.

P.S.: I've also tried to declare the pkg (used in both proj_A and proj_B) only in a third library called "work" but the tool "translates" it into the library where the package is being used...that is, in proj_A "work.pkg" will be seen as "proj_A.pkg" and "proj_B.pkg" in proj_B...

 

[TrickyDicky]

This is all down to strong typing in VHDL. In VHDL, the following are not the same type, but are closely related types:

type a_t is array(natural range <>) of integer;
type b_t is array(natural range <>) of integer;

So, if I have the following signals:

signal a : a_t;
signal b : b_t;

I cannot simply write
a <= b;

but I can write
a <= a_t(b);

The problem you are having is you have now declared a component ent_proj_A using project B's types. But the entity itself uses the types from project b, so it cannot map the component ports to the entity ports because the types do not match. I see why you either cant just call in project A package in project B, or make another package with types common to all packages. An easy way round this will be to not use components at all and use direct instantiation (which is a good thing, because you dont need to maintain 2 copies of the same entity declaration) but you will still need to include both project's libraries. and to complicate things, because you have the same types named in both packages, you will have to use direct reference to make them work, or you will not have visibility on either:

a <= proj_a.a_t(b);
b <= proj_a.a_t(a);

As for your question about work - work is the deafault package in VHDL - it always refers to the local library, as you have discovered.

 

[lablasa]

Maybe I didn't understand...or simply I didn't exlpain as I wanted...
I'm using same types...that is

LIBRARY proj_B;
USE proj_B.pkg_B.ALL;

LIBRARY proj_A;

entity ent_proj_B is
port(
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(31 downto 0)
);
end ent_proj_B;

architecture struct of ent_proj_B is

signal input_B: a_8bit(3 downto 0);
signal output_B: a_31bit(3 downto 0)

component ent_proj_A
port (
input_A: a_8bit(3 downto 0);
output_A: a_31bit(3 downto 0)
);
end component;

begin

inst_A: ent_proj_A
port map(
input_A => input_B,
output_A => output_B
);

input <= input_B(0);
output <= output_B(0);

end struct;

maybe direct instantiation could work but...I'm using HDL Designer and I don't know how to implement it...I don't even know if it's possible

 

[TrickyDicky]

the problem is a_8bit in project A is NOT the same type as a_8bit in project B. They are not directly compatible, but they are similar types, so you can type cast between them.

The problem is that in your component declaration:

component ent_proj_A
port (
input_A: a_8bit(3 downto 0);
output_A: a_31bit(3 downto 0)
);
end component;

Because you have only included pkg_B, the ports declared on the componenet are from pkg_B, but on the actual entity they are from pkg_A, and as I said before, these types are NOT the same, which is why you are getting the error you are getting, because it cannot map the ports on your component declaration to those on the entity declaration. The only way to solve this is to include pkg_A in ent_proj_B, and to avoid hiding all the types with the same names, you have to qualify EVERYTHING in your code AND do type conversion. There is NO way round this with the current setup, whether you do direct instantiation or not.

so, here is your modified code, with the changes that will make it work:

LIBRARY proj_B;
USE proj_B.pkg_B.ALL;

LIBRARY proj_A;
use proj_A.pkg_A.all;

entity ent_proj_B is
port(
  input : in std_logic_vector(7 downto 0);
  output : out std_logic_vector(31 downto 0)
);
end ent_proj_B;

architecture struct of ent_proj_B is

  signal input_B: proj_B.pkg_B.a_8bit(3 downto 0);
  signal output_B: proj_B.pkg_B.a_31bit(3 downto 0)

  component ent_proj_A
  port (
    input_A: proj_A.pkg_A.a_8bit(3 downto 0);
    output_A: proj_A.pkg_A.a_31bit(3 downto 0)
  );
  end component;

begin

inst_A: ent_proj_A
port map(
  input_A => proj_A.pkg_A.a_8bit(input_B),   --you can do this because they are similar types
  output_A => proj_A.pkg_A.a_8bit(output_B)
);

input <= input_B(0);
output <= output_B(0);

end struct;

It is not pretty, but is the only way to make it work currently.

I would recommend creating a library called "common" or something, and in it put a package that contains all of the types common to both libraries to get around this mess.

 

[lablasa]

I absolutley agree with you: I've modified my code adding everywhere proj_B.pkg_B.a_nbit or proj_B.pkg_B.a_nbit and doing conversione where necessary...a terrible work....
As you suggested, I think I'll use a third common library for the package...as I did with "work" library (I chose "work" just to simplify ISE project: it was just a way to avoid adding a new folder to the project...)
thank you!