problem with SDF backannotation in scirocco

[a.pareek]

I am facing a problem with back-annotating the SDF file generated by encounter into scirocco for a post layout simulation. I read in the sdf file using DC and generated a new sdf but i am getting errors. Well, I can back-annotate the sdf files for combinational circuits but not for sequential circuits. Can anyone suggest any solution.

Thanks
Abhishek

 

[jjww110]

please give more information

 

[a.pareek]

I was trying to implement a Baud Rate Generator which was originally designed in VHDL in encounter. So, I first synthesized it using Synopsys DC, created a structural Verilog netlist and generated a timing file(sdc) for using in encounter. I was able to place and route it in encounter and generate the SDF in it. Then I used the .db file created by DC and read in the SDF generated by the encounter and generated another SDF because the SDF generated by encounter cannot be read by the (Scirocco)simulation tool. I also created a structural VHDL netlist to simulate it.
When I try to simulate it using the following command in scirocco, it gave me error.

scsim -sdf /<testbench entity name>/UUT/:filename.sdf

The simulation tool was not able to find a register in the testbench that was mentioned in the sdf file. I will post the code, testbench and the error that it generated today.
By the way, I am able to do a functional simulation but I get errors in all the post synthesis simulation.

Thanks

 

[aji_vlsi]

When I try to simulate it using the following command in scirocco, it gave me error.

scsim -sdf /<testbench entity name>/UUT/:filename.sdf

The simulation tool was not able to find a register in the testbench that was mentioned in the sdf file. I will post the code, testbench and the error that it generated today.
By the way, I am able to do a functional simulation but I get errors in all the post synthesis simulation.

Thanks

Looks like your SDF had some register name not found in netlist. Post the exact error, how many have you got? It may be OK to have few, annotation might still happen, ideally you would have zero such errors though.

HTH
Ajeetha, CVC
www.noveldv.com/old_page

 

[a.pareek]

I tried doing a smaller design like a counter and its giving me similar errors as in Baud rate generator. I am listing the errors here.
I am attaching the sdf file and the structural vhdl file also the testbench for the counter. I am getting the following errors. The simulator fails to parse the sdf file.
Please remove the .jpg extension before openoing the file. I had to append it because it wouldn't let me attach .sdf and .vhd files.

The exact command I use to invoke the simulator is

./scsim -sdf /tb_counter/UUT/:counter_ban.sdf

The errors that I get are as follows:

ERROR: simulation scsim Elab -vhdl-251
(SDF file: counter_ban.sdf Line: 18) instance /TB_COUNTER/UUT/U33 not found

ERROR: simulation scsim Elab -vhdl-251
(SDF file: counter_ban.sdf Line: 18) reference port A not found; statement ignored

It gives same error for all the instances in sdf at lines 18 through 57, 63, 72, 84, 96, 108, 120, 132, 144, 153, 163 and 174. All these lines contain instantiation of one or the other component of the design.

Please let me know if you need anymore information.

Thanks