nasroulm
Newbie level 3
Hello,
I am using TSMC0.25Lo[Logic] to make an ASIC chip using the standard cell libraries. After synthesis and importing into the cadence I am trying to run LVS on my design.
The problem I am running into is the cells are front end view so I can't see the guts of them and I want to tell Assura to stop at cell level when extracting the netlist from layout and layout.
Has any one have any idea, how to do that?
Thank you
Mo
I am using TSMC0.25Lo[Logic] to make an ASIC chip using the standard cell libraries. After synthesis and importing into the cadence I am trying to run LVS on my design.
The problem I am running into is the cells are front end view so I can't see the guts of them and I want to tell Assura to stop at cell level when extracting the netlist from layout and layout.
Has any one have any idea, how to do that?
Thank you
Mo