lokeyh
Advanced Member level 4
Question on Verilog
Hi all,
I am new to verilog. I have a problem.
I have a port on a module that is defined as inout. Sometimes, I need to drive it with a signal and sometimes, the port need to drive a signal. VCS gives errors when I drive the port with register. What should I write in the testbench to avoid that error.
Thanks.
Hi all,
I am new to verilog. I have a problem.
I have a port on a module that is defined as inout. Sometimes, I need to drive it with a signal and sometimes, the port need to drive a signal. VCS gives errors when I drive the port with register. What should I write in the testbench to avoid that error.
Thanks.