Problem with MOS Bulk Routing Parasitic Resistance Extraction

[Stepan Sutula]

Hi,

During the Spectre netlist generation process, I have found out that the Assura QRC extractor includes the parasitic resistances of the MOS transistor bulk routing in the extraction view:
rg58 (vdda \5\:vdda) resistor r=24.5376 c=0
But, it skips connecting this parasitic resistor to the bulk of the transistor:
M10 (\3\:vout \5\:nclk \2\:vin vdda) p_lv_18_mm w=1.92e-06 l=2.4e-07 ad=2.224e-13 as=2.224e-13 pd=2.0u ps=2.0u m=(1)*(1)
From the line above, you can see that it circumvents the parasitic resistor and connects the bulk directly to the polarization net vdda (NOT \5\:vdda)
As a result, the simulation netlist generated from this extracted view is also incorrect.

I have tried two different technologies with two different design kits and both have the same issue. Two kits are:
1. Virtuoso Design Environment version IC6.1.3.500.13 with Cadence Extraction QRC - Parasitic Extractor - Version 8.1.4-p002.
2. Virtuoso Design Environment version IC6.1.5-64b.500.132 with Cadence Extraction QRC - Parasitic Extractor - Version 11.1.2-p106.

Is there any way to fix this problem? Can it be done by modifying the configuration script or updating the kit?

Thanks,
Stepan.

 

[sat]

There are more than one ways to do that.
QRC substrate handling methodology has been changed sin 8.x [exact version number I forgot] - there are detailed and good technical reasons backed by many big design house and fab. In new versions of QRC, the back-gate of MOS will get ideal VSS/VDD [based on psub,nwell in NMOS/PMOS] - by default, unless proper methodology is in place.

Few recommendations :
- Check your PDK docs [Readme etc]
- Check LVS extract rule [if substrate is stamped - check next line - else skip next line]
- Look for stamp=1 or stamp=2 stuffs in p2lvsfile /or/ layer_setup in QRC-tech-dir [ if not there, you can add and do Techgen compilation process once again ]
- If above is not there - use ignorevias thing.. [ this has to do with how substrate gets the subnet - even when not stamped ]

In physics, substrate parasitics separately can also be extracted - it is a 3D mesh - which needs foundry provided doping profiles and so on.. QRC is the only product that has that capability at the chip level - been used by some RF design houses.