vhdl problem.
this is a little more complex...
when we are in satate "x" if some conditions are occur, "bar" goe high and we travel to state "y",
in this state if bar='1' or latch='1' some transactions are gonna happen on the bus and then we travel to state "z".... it's not the problem of scheduling in processses i think...
i think tkbits hits the point, but i still don know why should it work without "or" and when we just "or" them every thing fails...
Added after 17 minutes:
the main problem is that i am a beginer in coding and working with these softwars i think...
let me say something more amazing in my design....
there was an internal signal in my design named "ghazgholang", it did not do its work properly,
then i declare an output port for it, just to see what happens on this signal during the simulation...
and then it's working!!!! i did not do any any other changes in the whole design but.....
now if i remove this "for-testing-purpose-output-port" ,again it does not work properly....
is it common problem in coding? plz help me please..