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Problem with "kuft" command in VHDL

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vahidkh6222

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hi all..
it is realy confusing!:!:
in part of my very large design,i wrote this, and it was working well:
Code:
latch <='1' when ((COMMAND(0) AND DATA_TRANSFER) and addr(2) and(not(addr(4) or addr(3))))='1' else '0';
then i wrote this, and it was working well:
Code:
bar<= '1' when ((COMMAND(0) AND DATA_TRANSFER) and addr(4) and (not(addr(3) or addr(2))))='1' else '0';
then i added this and i still can not see the desired output....

Code:
kuft<= bar or latch;
the output is remain on '0' value forever.(althoug i see inputs are in their desired state...)
help me plz!!
( i tried many other ways, but i thought that at least in this very very simple method there should not be any problem...but i'm gonna die!!)

i am using xilinx ise6.2 with modelsim se plus 6.0
 

EDALIST

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Re: vhdl problem.

i think your writing is confusing you shoud write :

bar <='1' when
((COMMAND(0)='1' AND DATA_TRANSFER='1')
and
(addr(4 downto 2) = "101" or addr(4 downto 2) = "111" or addr(4 downto 2) = "100")
else '0';
latch <='1' when
((COMMAND(0)='1' AND DATA_TRANSFER='1')
and
(addr(4 downto 2) = "011" or addr(4 downto 2) = "111" or addr(4 downto 2) = "001")
else '0';
 

vahidkh6222

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vhdl problem.

tnx EDALIST,
but at first i had tried this method too,...
i want to know, why it does not work when i just OR two readily working signals.... can it be the software fault? for example XST, or modelsim?
 

tkbits

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Re: vhdl problem.

Are you using "kuft" to control (directly or indirectly) COMMAND, DATA_TRANSFER, or addr?
 

vahidkh6222

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vhdl problem.

yes, somehow.....
command is a signal which varies in each state of a state machine....
kuft is the grant to travel from one of the states to another one.... does it make problems? wut shoud i do then?
 

semiconductorman

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Re: vhdl problem.

I am unable to 'see' the problem since this is only a 3 line sinppet of your code . Just pinning down my thoughts . Your 'bar' and 'latch' are both signals they will be assigned the values of '1' only on reaching the end of your 'process' and if you try 'or'ing these 2 signals then inside of the same 'process' you will get '0' since they are yet to be assigned. So go ahead and declare the oring in another process with sensitivity list of bar and latch. I have lost touch with vhdl or a long time so forgive me if I have confused you. Let me know if you understand what i am trying to say and also if this works for you.
 

vahidkh6222

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vhdl problem.

this is a little more complex...
when we are in satate "x" if some conditions are occur, "bar" goe high and we travel to state "y",
in this state if bar='1' or latch='1' some transactions are gonna happen on the bus and then we travel to state "z".... it's not the problem of scheduling in processses i think...

i think tkbits hits the point, but i still don know why should it work without "or" and when we just "or" them every thing fails...

Added after 17 minutes:


the main problem is that i am a beginer in coding and working with these softwars i think...
let me say something more amazing in my design....
there was an internal signal in my design named "ghazgholang", it did not do its work properly,
then i declare an output port for it, just to see what happens on this signal during the simulation...
and then it's working!!!! i did not do any any other changes in the whole design but.....
now if i remove this "for-testing-purpose-output-port" ,again it does not work properly....

is it common problem in coding? plz help me please..
 

noloser

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vhdl problem.

why not use FSM model for it. it would be less confusing in that case, isn't it? just test for the require inputs then decide the next state to go, and create the desired output within that sate without using complicated calculation as output for every state are normally fixed in nature.
 

vahidkh6222

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vhdl problem.

the state machine is implementation of PCI specification, then i dont want to manipulate it....
 

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