[PIC] Problem with Interrupt - 12F683 MikroC code

[mm_pk1]

Dear all,

I am new on PIC12x. Code continuously toggles the GP0 of 12F683 and whenever interrupt (INT) is invoked, GP1 toggles. The problem is that interrupt is invoked only once, and it seems that after executing the ISR, control does not return back to the main function. When interrupt is invoked first time, GP1 toggles but after that LED blinking on GP0 stops. Following is the code and Proteus schematic is also attached for reference please:

unsigned char a=0;

void interrupt ()
{
   GPIO.F1 = ~a;     //Toggle GP1 at each interrupt occurrence 
   INTCON.F0 = 0;   //Clear INT flag
}

void main()
{
     ANSEL = 0;
     CMCON0 = 7;
     TRISIO.F0 = 0;     //Continuous blinking LED on this port
     TRISIO.F1 = 0;     //This port toggles whenever interrupt occurs
     TRISIO.F2 = 1;     //Making GP2 as input for interrupt

     while(1)
     {
        INTCON = 0xD0;   //Enable Global interrupt and INT
        {
           GPIO.F0 = 0;    
           Delay_ms(100);
           GPIO.F1 = 1;
           Delay_ms(100);
       }
     }
}

 

[aruipksni]

from looking at your code - it look like you don't blink each one of the leds....

 

[betwixt]

     while(1)
     {
        INTCON = 0xD0;   //Enable Global interrupt and INT
        {
           GPIO.F0 = 0;    
           Delay_ms(100);
           GPIO.F1 = 1;  [COLOR="#FF0000"]<<<<<<<< Did you mean GPIO.F0 = 1; ??????[/COLOR]
           Delay_ms(100);
       }
     }

In any case, it's best to set the value of INTCON outside the loop and enable the INTE interrupt bit before GIE (do it in two lines of code).

Brian.

 

[swapan]

Your code shows that External Interrupt is enabled by INTCON = 0xD0, whereas in ISR, you are clearing the INTCON.F0 i.e. port change interrupt flag bit. The INTCON.F1 bit (External interrupt flag bit) should be cleared instead INTCON.F0 bit. The reason that control does not return from ISR is - the concerned interrupt flag bit is not cleared, thus forcing the control to remain in ISR indefinitely.