[SOLVED] Problem with `include in verilog

[kjm]

Hi,
I am trying to include "tasks.v" file in my testbench file "tb_data.v" . after reg,wire and parameter declarations, I have include this file ('include "tasks.v"). But it is giving error (expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].).

the tasks.v file looks like this:
task prep_req;
begin
request <= 1'b1;
@(posedge i_SymbolClk)
request <= 1'b0;
end

endtask // prep_req

There are other similar tasks like this in "tasks.v" file. Both the files (testbench + tasks) are in same folder. Please help.
Thanks

 

[yx.yang]

Maybe, you need include this task between the module / endmodule (not outside of it).
module a ();

input
output
wire
reg

`include "task.v"

endmodule

And when you compile your RTL codes, you can't include task.v in the file list (the compile tool will merge it into "module a" automatic).

 

[kjm]

Maybe, you need include this task between the module / endmodule (not outside of it).
module a ();

input
output
wire
reg

`include "task.v"

endmodule

And when you compile your RTL codes, you can't include task.v in the file list (the compile tool will merge it into "module a" automatic).

I included the task between module/endmodule. But I was including it in the file list during compilation. That's why I was getting error...
SOLVED.

Thanks a lot