problem with if generate statement

[kakarala]

HI i am trying to use if generate statement . Here i declared rp as constant array in a package and rp_x as a signal. When i am synthesizing it gives me the following error

ERROR:HDLParsers:1305 result of operator = is not static.


A :if rp(rp_x) = 1 generate
p1 <= p-stepsize;
sad02 : SAD4X4 port map(clk => clk, rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q,sad => sad1);
end generate ;

 

[permute]

every term in "rp(rp_x)" must be constant. generates aren't going to work the way you want them to.

 

[TrickyDicky]

Generates are filled out at elaboration time, not run time, hence why they need to be static. The implemented SAD4X4 cannot be implemented and removed on the fly.

 

[hareshcooleng]

I think that u can't using both blocking and non blocking statement in your program. try to use the if rp(rp_x) <= 1 generate.

 

[TrickyDicky]

I think that u can't using both blocking and non blocking statement in your program. try to use the if rp(rp_x) <= 1 generate.

you cannot use a signal in a generate statement!

 

[hareshcooleng]

sorry for that ans. I am new member of that forum and also i know only for verilog hdl that's why i give that ans.