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Problem with FPGA Design

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alexma

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aggregate expression cannot be scalar type

I have a problem when program the FPGA using VHDL connecting to A to D Converter (TLC548I), the error came out as follow:

** Error: H:/D4/FPGA1/ADCmem.vhd(50): Aggregate expression cannot be scalar type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(53): Cannot resolve indexed name as type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(56): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(75): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(88): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(101): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(114): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(127): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(140): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(153): Assignment target type std_ulogic_vector is different from expression type std_logic.
** Error: H:/D4/FPGA1/ADCmem.vhd(166): Assignment target type std_ulogic_vector is different from expression type std_logic.



the (incomplete) codes are as follow:

library ieee;
use ieee.std_logic_1164.all; -- include definition of std_logic
entity adc is
port (input,clock: in std_logic; ioclock, scl_out, sda_out ,cselect: out std_logic;
output : inout std_logic);

end entity adc;

architecture behaviour of adc is
type state is ( s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal current_state, next_state : state;
signal ioclk, scl : std_logic :='0';
signal sda : std_logic := '1';
signal cs :std_logic := '1';
signal ram_CS,ram_WE,ram_OE : std_logic;
signal addr : integer range 0 to 7;

begin
seq: process(clock) is
begin

ioclock <= ioclk;
scl_out <= scl;
sda_out <= sda;

cs <='1'; --initial value
cselect <= cs;

ioclk <= not ioclk after 250 ns;
ioclock <= ioclk;
scl <= not scl after 250 ns;
scl_out <= scl;

cs <= '0';
cselect <= cs;
-- wait for 1400 ns; -- not sure
current_state<= s0;

if falling_edge(clock) then
current_state <= next_state;
end if;
end process seq;

com: process(current_state,cs,ioclk, addr,ram_CS, ram_WE,ram_OE) is
type ram_array is array (0 to 7) of std_ulogic_vector(7 downto 0);
variable mem: ram_array;
variable cnt: integer := 0;

begin
output <= (others => 'Z');
if ram_CS = '0' then
if ram_OE = '0' then
output <= mem(addr);
elsif ram_WE = '0' then

mem(addr) := output;
end if;
end if;

case current_state is
when s0=>
if (cs = '0') and (ioclk = '0') then

while not (cnt = 12) loop
if rising_edge(clock) then
cnt := cnt + 1;
end if;
end loop;

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 0;

mem(addr) := output; -- not finish
next_state <= s1;
else next_state <= s0;
end if;

when s1=>
if (cs= '0') and (ioclk = '0')then

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 1;

mem(addr) := output; -- not finish
next_state <= s2;
else next_state <= s1;
end if;

when s2=>
if (cs= '0') and (ioclk) = '0'then

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 2;

mem(addr) := output; -- not finish
next_state <= s3;
else next_state <= s2;
end if;

when s3=>
if (cs= '0') and (ioclk = '0')then

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 3;

mem(addr) := output; -- not finish
next_state <= s4;
else next_state <= s3;
end if;

when s4=>
if (cs= '0') and (ioclk = '0')then

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 4;

mem(addr) := output; -- not finish
next_state <= s5;
else next_state <= s4;
end if;

when s5=>
if (cs= '0')and(ioclk = '0') then

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 5;

mem(addr) := output; -- not finish
next_state <= s6;
else next_state <= s5;
end if;

when s6=>
if (cs= '0') and (ioclk = '0')then

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 6;

mem(addr) := output; -- not finish
next_state <= s7;
else next_state <= s6;
end if;

when s7=>
if (cs= '0') and (ioclk = '0')then

ram_CS <= '0';
ram_OE <= '1';
ram_WE <= '0';
addr <= 7;

mem(addr) := output; -- not finish
--next_state <= s0;
next_state <= s8;
cs <= '1';
cselect <= cs;
else next_state <= s7;
end if;

when s8 =>
-- if scl = 1 then
-- sda <= 0;
next_state <= s0;


end case;
end process com;
end architecture behaviour;
 

cippalippa

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aggregate expression can not be scalar std_logic

An error is because you can try to assign mem (array of std_ulogic) with signal output (std_logic) and viceversa but the types are different; so you must convert the typer before or use std_logic for mem array.

Daniele
 

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