thanks for your reply ads_err, yes I have already added the input.txt to the directory as you said but the error persist again. that is my code, perhaps I wrote something wrong:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
library STD;
use STD.textio.all;
---------------------------------------------------------------------
entity tb_additionneur is
end tb_additionneur;
---------------------------------------------------------------------
architecture TB of TB_additionneur is
component additionneur
port(
clock: in std_logic;
reset: in std_logic;
inp1: in std_logic_vector(3 downto 0);
inp2: in std_logic_vector(3 downto 0);
inp3: in std_logic_vector(3 downto 0);
Som
ut std_logic_vector(5 downto 0)
);
end component;
-------fichier de testbench--------------
------------------------------------------
signal T_clock: std_logic;
signal T_reset: std_logic;
signal T_inp1: std_logic_vector(3 downto 0);
signal T_inp2: std_logic_vector(3 downto 0);
signal T_inp3: std_logic_vector(3 downto 0);
signal T_som: std_logic_vector(5 downto 0);
begin
U_additionneur:additionneur
port map(T_clock, T_reset,T_inp1,T_inp2,T_inp3,T_som);
-- procedure d'horloge-------------------
process
begin
T_clock <= '0';
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;
--------------------------------------------
---------- entree a partir de fichier text-------------
read_input
rocess
file fileIn : text open read_mode is "Input.txt";
-- les variables de lecture
variable read_len:natural;
variable ligne: line;
variable good_number : boolean;
-- les variables d'entrées
variable V_inp1,V_inp2,V_inp3 : std_logic_vector(3 downto 0);
begin
FILE_OPEN(fileIn, "Input.txt" );
while not endfile(fileIn) loop
-- lecture de la ligne
readline(fileIn, ligne);
read(ligne,V_inp1);
read(ligne,V_inp2);
read(ligne,V_inp3);
T_inp1 <= V_inp1;
T_inp2 <= V_inp2;
T_inp3 <= V_inp3;
end loop;
wait;
end process;
T_reset <= '1' after 0 ns, '0' after 100 ns ;
end TB;