problem with division in vhdl code

[velu.plg]

this my code.

entity test is
Port ( en : in std_logic;
a : inout integer;
c : out integer);
end test;
architecture Behavioral of test is
begin
process(en)
begin
if(en='1')then
a<=a+1;
c<=a/10; ---49
end if;
end process;
end Behavioral;

error :line 49: Operator <DIVIDE> must have constant operands or first operand must be power of 2

how can i solve.

 

[TrickyDicky]

The synthesis has given you the answer. Xilinx doesnt support the divide operator when it cannot create a constant value or place a bit shift (as A/2^N is a bit shift).
You need to use the divider IP core.

Also: why is a an inout? A cannot be an inout because integer is not a resolved type, so your code is illegal.

 

[velu.plg]

there is any other method available for division without using ip core?

 

[TrickyDicky]

Altera quartus will accept this code I think. but it just generates an IP code with 0 pipelining.

But in xilinx, I dont think so.

 

[velu.plg]

i have only spartan kit.

how can i display integer j (ex:123) in lcd display.
this j's function is
when switch on j=j+1;

give any idea.

 

[TrickyDicky]

You will need an LCD driver. I suggest reading up on the datasheet for the LCD module. A reference design that may have shipped with the board should show the LCD working.