hi i am using the dcm in virtex 2 pro fpga..i have an i/p of 100mhz clk and i want 125mhz clk. the problem is when i simulate it is working fine but it is failing when downloaded onto fpga.i could not get 125mhz clk. so can anyone give me suggestions
It should work fine. What did you get instead of a 125 MHz clock?
If you can show us a small project that demonstrates the problem, maybe someone can hep you debug it.
Also say which tools you used.
I specified all the parameters...i am using xilinx ise 7.1 with sp4..the post synthesis simulation is working but when downloaded onto chip it is not working..i mean i am not getting any output at the clockfx on the board..but i am getting clk0 output