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problem with DAC for spartan 3E

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asraf

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i having problem with my verilog DAC..can anyone help me plsssssssss...

module dac5(clk,reset,dac_mosi,dac_sck,dac_cs,spi_ss_b,amp_cs,ad_conv,sf_ce0,fpga_init_b);

input clk;
input reset;

output dac_mosi;
output dac_sck;
output dac_cs;
output spi_ss_b;
output amp_cs;
output ad_conv;
output sf_ce0;
output fpga_init_b;

reg dac_mosi;
reg dac_sck;
reg dac_cs;
reg spi_ss_b;
reg amp_cs;
reg ad_conv;
reg sf_ce0;
reg fpga_init_b;

reg [31:0] data;
reg [4:0] count;
reg [2:0] state;
reg [1:0] kireclk;



localparam idle=3'b000,
ready=3'b001,
dummy=3'b010,
send=3'b011,
check=3'b100;

initial
begin
data<=32'b00000000001111111000000000000000;
count<=5'd31;
kireclk<=2'b0;
end

always@(posedge clk)
begin
spi_ss_b<=1'b1;
amp_cs<=1'b1;
ad_conv<=1'b0;
sf_ce0<=1'b1;
fpga_init_b<=1'b1;
end

always@(posedge clk)
begin
if(kireclk==2'b11)
kireclk<=2'b0;
else
kireclk<=kireclk+1'b1;
end


always@(posedge clk)
begin
case(state)
idle:
begin
count<=5'd31;
dac_sck<=1'b0;
dac_cs<=1'b1;
state<=ready;
end

ready:
begin
dac_sck<=1'b0;
dac_cs<=1'b0;
dac_mosi<=data[count];
state<=dummy;
end

dummy:
begin
state<=send;
end

send:
begin
dac_sck<=1'b1;
if(kireclk==2'd3)
state<=check;
else
state<=send;
end

check:
begin
dac_sck<=1'b1;
if(count==5'd0)
state<=idle;
else
count<=count-1'b1;
state<=ready;
end

endcase
end

endmodule


UCF file:


NET "ad_conv" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "amp_cs" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "dac_cs" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "dac_mosi" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "dac_sck" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "fpga_init_b" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
NET "sf_ce0" LOC = "D16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
NET "spi_ss_b" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;

---------- Post added at 19:48 ---------- Previous post was at 19:41 ----------

here i attached my code with comment

module dac5(clk,reset,dac_mosi,dac_sck,dac_cs,spi_ss_b,amp_cs,ad_conv,sf_ce0,fpga_init_b);

input clk;
input reset;

output dac_mosi;
output dac_sck;
output dac_cs;
output spi_ss_b;
output amp_cs;
output ad_conv;
output sf_ce0;
output fpga_init_b;

reg dac_mosi;
reg dac_sck;
reg dac_cs;
reg spi_ss_b;
reg amp_cs;
reg ad_conv;
reg sf_ce0;
reg fpga_init_b;

reg [31:0] data;
reg [4:0] count;
reg [2:0] state;
reg [1:0] kireclk;



localparam idle=3'b000,
ready=3'b001,
dummy=3'b010,
send=3'b011,
check=3'b100;

initial
begin
data<=32'b00000000001111111000000000000000;
count<=5'd31;
kireclk<=2'b0;
end

always@(posedge clk)//initial declaration to enable DAC
begin
spi_ss_b<=1'b1;
amp_cs<=1'b1;
ad_conv<=1'b0;
sf_ce0<=1'b1;
fpga_init_b<=1'b1;
end

always@(posedge clk)
begin
if(kireclk==2'b11)
kireclk<=2'b0;
else
kireclk<=kireclk+1'b1;
end


always@(posedge clk)
begin
case(state)
idle:
begin
count<=5'd31;//the SPI must entered with MSB
dac_sck<=1'b0;//the clk is still 0 when no data
dac_cs<=1'b1;//initial value is 1
state<=ready;
end

ready:
begin
dac_sck<=1'b0;
dac_cs<=1'b0;//ready to receive data
dac_mosi<=data[count];//dac_mosi is 1 bit register so i transfer 1 bit at one time
state<=dummy;
end

dummy:
begin
state<=send;
end

send:
begin
dac_sck<=1'b1;//the dac_sck must stay at high state for atleast 4ns..so i count 4 times
if(kireclk==2'd3)
state<=check;
else
state<=send;
end

check:
begin
if(count==5'd0)
state<=idle;
else
count<=count-1'b1;
state<=ready;
end

endcase
end

endmodule
 

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