fighter212
Newbie level 4
hi all,
i'm encountering a very strange problem about clock in my design. the clock net "clk" is connected directly to the CP port of a FF. when i observe the net "clk", it works normally. but when i observe the CP port of the FF, it holds logic 1.
if i run simulation without loading .sdf, everything works normally.
here is the waveform from debussy. who can help me.
i'm encountering a very strange problem about clock in my design. the clock net "clk" is connected directly to the CP port of a FF. when i observe the net "clk", it works normally. but when i observe the CP port of the FF, it holds logic 1.
if i run simulation without loading .sdf, everything works normally.
here is the waveform from debussy. who can help me.