attempt to annotate to non-existent source port
in my design i used some ram models which are descripted in behaviour level and will be replaced by hardware core when tape out. in netlist these ram models remain in behaviour level. So there are some warnings like this:
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port DOx6x at scope level tb_chip.chip.u0.epinf.ep0_rx_fifo.ram0.sram2_64x8.
ncelab: *W,SDFAND: Attempted INTERCONNECT annotation to non-existent destination port RAx5x at scope level tb_chip.chip.u0.epinf.ep0_rx_fifo.ram0.sram2_64x8.
some other warnings are like this:
ncelab: *W,SDFNGL (e:\project\smic\zero\sdnrq2.v,87|40): Attempt to annotate negative timing check limit in instance (tb_chip.chip.u0.rst_local_reg), yet -NEG_TCHK not specified, setting to 0.
$hold (posedge CP &&& (SC==1'b1),posedge SD &&& (SC==1'b1),th_cp_sd_l,notifier);
ncelab: *W,SDFNL1 (e:\project\smic\zero\decrq2.v,95|74): Attempt to annotate a negative value to a 1 limit timing check in instance (tb_chip.chip.u0.eeprom_if.\counter_start_stop_reg[0] ), setting to 0.
$recovery (posedge CDN &&& (ENN==1'b0),posedge CP &&& (ENN==1'b0),tsu_cdn_h_cp,notifier);
my synthesis and simulation tool is synopsys design compiler and cadence nc-verilog.