Re: Clock counter.
Hello.
How about something like this
entity timer is
port(clk0, clk2x, a ,b in std_logic; sel, f out std_logic);
end timer;
architecture primary of timer is
signal bias std_logic;
begin
if (clk2x'event and clk2x='1') then
sel <= (not sel) or bias;
end if;
if (clk0'event and clk0='1' then
bias<=sel;
end if;
if (sel='0') then
f<=a;
elsif
f<=b;
end if
end primary
Added after 4 hours 10 minutes:
or, even better,
entity timer is
port(clk, a ,b: in std_logic; sel, f: out std_logic);
end timer;
architecture primary of timer is
signal Q1, Q2: std_logic;
begin
process
begin
wait until CLK'event
if clk='1' then
Q1<=not Q1
else
Q2<=Q1
end if
sel <= Q1 xor Q2;
if (sel='0') then
f<=a;
elsif
f<=b;
end if
end process
end primary