Problem with clock counter in a mux design

[suddy72]

Hi guys ,

I am designing a mux, i want the select line to be set to 1 on every rising edge and 0 on every falling edge, that way the mux is changing twice every clock cycle. I seem to be having problems getting this to work, any one have any simple code that will do what i require.

thanks

stuart

 

[Iouri]

Clock counter.

What is clock frequency?

 

[MGT78000]

Re: Clock counter.

Hello.

How about something like this

entity timer is
port(clk0, clk2x, a ,b in std_logic; sel, f out std_logic);
end timer;

architecture primary of timer is
signal bias std_logic;
begin
if (clk2x'event and clk2x='1') then
sel <= (not sel) or bias;
end if;
if (clk0'event and clk0='1' then
bias<=sel;
end if;
if (sel='0') then
f<=a;
elsif
f<=b;
end if
end primary

Added after 4 hours 10 minutes:

or, even better,

entity timer is
port(clk, a ,b: in std_logic; sel, f: out std_logic);
end timer;

architecture primary of timer is
signal Q1, Q2: std_logic;
begin
process
begin
wait until CLK'event
if clk='1' then
Q1<=not Q1
else
Q2<=Q1
end if
sel <= Q1 xor Q2;
if (sel='0') then
f<=a;
elsif
f<=b;
end if
end process
end primary

 

[kanagavel_docs]

Re: Clock counter.

Hi,

Just check this logic..

module counter(
reset,
clock,

mux0_in,
mux1_in,

mux_out)


input reset;
input clock;

input mux0_in;
input mux1_in;

output mux_out;

wire mux_en;
wire mux_out;

reg pos_flop;
reg neg_flop;

assign mux_en = pos_flop ^ neg_flop;
assign mux_out = (~mex_en) ? mux0_in : mux1_in;

//reset should be released in the low period of the clock
always @(posedge clock or negedge reset)
if(!reset)
pos_flop <= 1'b0;
else
pos_flop <= ~pos_flop;


always @(negedge clock or negedge reset)
if(!reset)
neg_flop <= 1'0;
else
neg_flop <= ~neg_flop;

endmodule

 

[echo47]

Clock counter.

Rising and falling edge of what? The clock?

How about using an ordinary 2-to-1 mux, with the select line connected to the clock?

What does "clock counter" mean in your subject line?

 

[MGT78000]

Re: Clock counter.

How about using an ordinary 2-to-1 mux, with the select line connected to the clock?

Can you do that on a Spartan 3E? That would make my life a lot easier.

 

[kanagavel_docs]

Re: Clock counter.

Hi,

It is not recommended to use clock/reset in combinational logics

 

[MGT78000]

Re: Clock counter.

It is not recommended to use clock/reset in combinational logics

What's the reason? Is the signal not strong enough?
But can you actually do it? And can you do the opposite, i.e. use a logic signal as the clock line on a latch?

 

[anoop12]

Re: Clock counter.

Hi MGT78000
The reason is that in combinational circuits, thje clock may get GATED, so it may lead to clock skew and related problems

 

[echo47]

Clock counter.

Yes, you can connect a clock to a mux select input, but ISE will probably give you a warning that the clock is feeding into asynchronous logic. That's usually bad design practice in an FPGA, due to the increased difficulty in achieving reliable timing, but I don't know your design or the purpose of your mux.

 

[nitin_ndg]

Clock counter.

echo47's reply posted if good 30 Oct 2007 10:59

 

[cherjier]

Re: Clock counter.

can do it in this way?

input ENABLE; <- optional
output MUX_SEL;
reg mux_sel_1, mux_sel_2;

assign MUX_SEL = (mux_sel_1 & !mux_sel_2) | (!mux_sel_1 & mux_sel_2 );

always @(posedge CLK or negedge RESET_N) begin
if (!RESET_N)
mux_sel_1 <= 1'b0;
else (ENABLE)
mux_sel_1 <= !mux_sel_1;
end

always @(negedge CLK or negedge RESET_N) begin
if (!RESET_N)
mux_sel_2 <= 1'b0;
else (ENABLE)
mux_sel_2 <= !mux_sel_2;
end

if that the case, u will have a MUX_SEL toggling at the same rate as the clock.
this will be a synchornous design by gating the register output rather than the clock.
the ENABLE signal is optional.. just for indication when to start toggling the mux select input.

i think this will have no problem in FPGA nor ASIC. if any issue please let me know as i'm a newbie as well.

 

[alzomor]

Re: Clock counter.

Hi

It seams that you are doing DDR Thing.
The FPGA library should include some ready made IP which Facilitates your work.
In Vertix4 there's a lot of such facilities.
You should check your FPGA user manual or library guide to see if it supports such IP

Salam
Hossam Alzomor
www(.)i-g(.)org