Arik
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vcd to saif conversion
Hi,
I'm trying to do gate level power analysis with Synopsys' Power Compiler. I do it exactly as stated in the Power Compiler's User Manual. After getting the backward SAIF file from gate-level simulation and compiling design with DC, I use the following commands:
The problem is that read_saif command doesn't annotate the all ports/nets/pins in the hierarchy i.e. in the lower levels of design hierarchy still remaining objects not been annotated.
NOTE: The backward SAIF file I'm getting from gate-level simulation contains the switching activity for the most top design.
Any comments appreciated !!!
Thanks in advance
Hi,
I'm trying to do gate level power analysis with Synopsys' Power Compiler. I do it exactly as stated in the Power Compiler's User Manual. After getting the backward SAIF file from gate-level simulation and compiling design with DC, I use the following commands:
Code:
reset_switching_activity
read_saif [i]backwrd_saif_file[/i] [i]instance_name[/i]
report_power
The problem is that read_saif command doesn't annotate the all ports/nets/pins in the hierarchy i.e. in the lower levels of design hierarchy still remaining objects not been annotated.
NOTE: The backward SAIF file I'm getting from gate-level simulation contains the switching activity for the most top design.
Any comments appreciated !!!
Thanks in advance