Problem with annotating switching activity !!!

[Arik]

vcd to saif conversion

Hi,

I'm trying to do gate level power analysis with Synopsys' Power Compiler. I do it exactly as stated in the Power Compiler's User Manual. After getting the backward SAIF file from gate-level simulation and compiling design with DC, I use the following commands:

reset_switching_activity
read_saif [i]backwrd_saif_file[/i]  [i]instance_name[/i]
report_power

The problem is that read_saif command doesn't annotate the all ports/nets/pins in the hierarchy i.e. in the lower levels of design hierarchy still remaining objects not been annotated.

NOTE: The backward SAIF file I'm getting from gate-level simulation contains the switching activity for the most top design.

Any comments appreciated !!!
Thanks in advance

 

[eda_wiz]

switching activity

The problem is that read_saif command doesn't annotate the all ports/nets/pins in the hierarchy i.e. in the lower levels of design hierarchy still remaining objects not been annotated.

NOTE: The backward SAIF file I'm getting from gate-level simulation contains the switching activity for the most top design

you should dump switching activity for all the nets in the design(all hierarchichal nets) to your saif file...

regards

 

[Arik]

vcd2saif dc_shell-t

Hi whizkid ,


I used the forward SAIF file for simulation which directs simulator to monitor the ports/nets/pins required for power estimation. Isn't it enough or I need to do anything else ???

 

[eda_wiz]

dumpsaif

Are u generating SAIF file from Netlist simulation??

 

[Arik]

power compiler switching file

Yep !!! I'm generating SAIF file from gate level simulation. Then I provide it to Power Compiler via read_saif command. The point is that report_saif command shows not 100% annotation for all sub_designs in my design hierarchy !!! Maybe it's normal, I don't know, but I'd like to know it exactly !!! I've read in Power Compiler's User Guide that SAIF file generated from gate level simulation enables annotation of all nets for the entire design. However I still have some nets not annotated in my design hierarchy. Besides I'm getting PWR-36, PWR-37 warnings !!! Can I ignore these warnings or I need to eliminate them ????

thanks for reply !!!!!

 

[eda_wiz]

capturing switching activity with ncsim

The point is that report_saif command shows not 100% annotation for all sub_designs in my design hierarchy !!! Maybe it's normal,

I donno whats wrong with your saif annotation, all I can say is that u are not dumping switching activity of all the nets..

Ok do like this.. dump VCD file of all the nets in the design in netlist simulation...
convert this VCD file to saif file with vcd2saif converter utility from synopsys.

read back this saif file to PwC and try report power..

 

[Arik]

$set_toggle_region( hierarchy

I don't want to use the VCD flow, instead I'm using the PLI interface which has all command set for capturing the toggle info.

$read_lib_saif()
$set_toggle_region()
$toggle_start()
$toggle_stop()
$toggle_report()
.....

The tools I'm using:

Simulator - Synopsys VCS
for Synthesis - Synopsys DC, Power Compiler

 

[amitdua]

annotating switching activity

Cadence NCSim simulator is able to dump backward SAIF natively!!
It also reads forward SAIF file. the support is for both gate and rtl.
I am not sure if any other simulator has this capability (including vcs).
The native support is very welcome as its much faster than PLI stuff
with other simulator!!!

This native support has been added to NCSim in IUS5.5 release through a tcl command "dumpsaif"

rgds
-Amit.

 

[computerstudent]

how to get switching activity from vcd

Hi to all and nice to join here
I'm serchning the software of Synopsys Power Compiler and did n't find it's linke to download yet
I neet it's and it is important for me
if anyone know where I can download it,please guide and help me
thanx alot

if anyone can help me
please contact me with this e-mail : semiticboy@walla.com


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