Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Problem with Altium Designer

Not open for further replies.


Advanced Member level 2
Oct 4, 2004
Reaction score
Trophy points
Activity points
altium print negative

The tool is very slow and get near to 1G ram, for a design that contain only 2 X 1148pin FPGA and 16 X PQFP100 with few other cap and res.:cry:

Is it true to say that tool is not suitable for component count more than 512?
If so, what other tool do you recommend?

altium negative print

I also use Altium to design big PCB like you.
It's not slow problem.
My PC spec. Intel Core2Duo, RAM 1G, Display card RAM 256M.

thermal vias altium

I suspect your speed problem is a result of the way you have your computer and the PCB Editor set up.

First - if you have a real-time virus checker running in the background, turn it off; better still, unload it. Some virus checkers slow the operation of graphics intensive CAD programs like Altium because they check every file access.

Next - In Altium Designer, go to Tools>>Design Rule Check>>Rules to Check. Right click in the right side of the dialog, and turn off online checking. Online checking just places markers where it detects a rule violation. In the early stages of design it is foolish to force the software to check every move and every placement. Note that turning off online checking doesn't turn off the design rules. They still will be enforced. You just don't get green markers everywhere.

Next - Altium Designer is a graphics intensive software. It needs a really good graphics card to work well. If you have one with DirectX 9.0c and Shader Model 3 support, the graphics can run much faster than with just plain GDI video. Make sure you have current drivers installed for your video card.

Next - Make sure you don't have other conflicting software running in the background. Nvidia's Desktop Manager is known to cause problems with CAD software. If you have it installed - uninstall it.

There are more tips, but these will get you started. Altium Designer can and has been used for boards much larger than yours. You just need a clean computer with enough power to get the best out of it.


    Points: 2
    Helpful Answer Positive Rating
adding drawing notes to altium designer 6

The main problem is at Annotate process, first annotate takes more than 15mon for a CPCI board, by small change like adding a component, annotate process report a big number of differences and try to match them again by adding and removing previous components, and again it takes more than 15min:cry:.

It seemes that link between schematic and pcb is missing! It is not a matter of CPU speed and GCard, I have tested this issue on many computers:|,

I am going to switch to PADS, what do you recommand?

excellon drill file altium

You need to understand how the process works in any EDA software. In Altium Designer, as in most EDA packages, everything is driven from the schematic.

Once the schematic is complete, you compile it. That is Altium's word for doing an electrical rules check, and generating the netlist. Once the schematic has been complied, you import the result into the PCB. The process of importing the design to the PCB is done via an Engineering Change Order (ECO) dialog that gives you the opportunity to accept or reject what is sent to the board.

If you change the annotation on the PCB, the changes have to be passed back to the schematic. If you are seeing a 15min delay on reannotation and coupling the information back to the schematic, the two documents must be out of syncronization. Altium Designer uses a unique identifier code (UID) to link the components on the PCB with the symbols in the schematic. Those UID's must be kept syncronized, or there is no way for the software to know how the schematic and PCB are related to one another. There is a tool on the menu for resyncronizing the UID's (Project>>Component Links).

The schematic and PCB editors in Altium Designer are tightly integrated. There is even a toggle function that automatically cross-selects an object in the schematic editor if it is selected on the PCB, and vice versa. It is the UID that allows that degree of integration.

Switch to PADS if you like. In my opinion, it is a more difficult tool tool to use. However, it will run on an older, slower, computer than Altium Designer requires. The reason is that it lacks the scope of tools, and video display options, available in Altium Designer.


    Points: 2
    Helpful Answer Positive Rating

dear House_Cat,

Thank you for your help and comments,

I am doing all project creation, annotation, ..., phases same as what you told and same as what we done for other previous succesful AD project. The problem is at CEO step, suppose that your fist annotation and placement was done(after 15min anyway), and now you have one new component(small resistor). In order to keep placed component, always we do a update process to assign a uniqe ID for new component and transfer it to PCB. In this project, for just one change, AD reports more mismatch even for unchanged and placed components, and in update process, remove and add the same component again!

I have other questions:
Suppose that you are asked to put a company logo on top-layer and open the mask sets for it: printing logo on CU. Which layer we must set? It is the same process which you may take for FID! the difference is that FID is a pad but logo is not!

The same situation exist for gold immersion!, how we can set masks and order the FAB to do gold immersion on some pads instead of hot air soldering layer?

negative print in altium 6

AD is DEFINATELY a resource hog.

Its a classic example of software developers going mad just because they can!, allocate big buffers yada yada....

Because the new PC these days have more resources does not mean the developers can abuse that by being LAZY and no longer optimize the code for responsiveness and efficiency and HOPE that users will keep buying the best and fastest hardware to get the software to still run at half the speed that 99SE did with the same job loaded.

I guess you already seen the size of files the new bloated code produced.

Compared to 99SE on the same PC its response time is night and day. And thats WITHOUT DX9/SM3 support!

So PC has made speed improvement of say X4 at least since 99SE to AD, but AD still is SLOWER today than 99SE WITH fancy new graphics rendering in hardware using DX.

Stone me if thats not a step backwards. no-one needs to be an EDA expert to work that one out.

So how much of a performance DECREASE has AD suffered for what is really an additional minimal feature set? WAY too much!

Try their pcb benchmark in GDI in AD and then on 99SE on same platform. Its an eye opener.

As for forward annotation, it looks like its scripted now and it can take a long time depending on net names used and what model the schematic has been built with. Way longer than it should take.

And whats with all this "compile" all the time? what a waste!

In 99SE you could leave the checking on all the time and fix errors as you go, why have a rule check then turn it off? Why wait on dense boards to find out that erros are all over the place and no route real estate left to fix it.

If the developers of AD were to be forced to take a step back, take stock of the mess they have made of a perfectly good product, rewrote the half assed features they have added so they actually work faster, the product would be almost unbeatable.


excellon altium

Johnson said:
dear House_Cat,

I have other questions:
Suppose that you are asked to put a company logo on top-layer and open the mask sets for it: printing logo on CU. Which layer we must set? It is the same process which you may take for FID! the difference is that FID is a pad but logo is not!

The same situation exist for gold immersion!, how we can set masks and order the FAB to do gold immersion on some pads instead of hot air soldering layer?

To place a logo on the copper, you need to create both the logo and a solder mask layer opening for the logo. To make the soder mask opening for the logo, just copy the copper layer pattern to the mask layer (copy and paste). Remember that the mask layer is negative, so anything you place on it is an opening.

For the gold plated pads, your fab drawing note would ask for selective gold in the areas indicated and you would show the pins that need to be gold plated... the fab would do pattern plating to apply the gold to those areas. You would probably also want to set the paste mask for those pads to a negative value equal to the size of the pad so the paste mask opening was closed for the gold plated pads during assembly.

As far as adding a single component goes, AD asks you if you want to try and match the unmatched components before the ECO is generated - you can usually just ignore that step and go directly to the ECO. You also have the option to select whether or not other things are changed on the board once you are in the ECO and waiting to execute it. If you are getting components deleted and readded, then there was some mismatch before you ran the ECO. Either you changed the designators (reannotated the whole schematic), or you changed something in a footprint somewhere.


    Points: 2
    Helpful Answer Positive Rating
laptop for altium

For the single/few components add in, we may edit the unique ID by ourself, then during updating, the mismatch problem will be solve.

altium designer pc specs

@ Frosty: I know this feeling :).. Had to improve software in the past, that was taking to much time: 2 Days on 28 PC's 1.5 GHz Pentium Machines. After starting from scratch it took 5 Minutes on ONE 1.5 GHz Pentium Machine. Why. Because they did everything you should not do and they had no clue what effect their software choices was having on the hardware. Writing to a file 2 or 3 bytes at a time, multiplying (-1) to change the sign of a number etc.... One problem is also C++ since they simply inherid all the classes without thinking. Allocating memory if it does not cost anything.. They should better start on 8 Bit Microcontrollers and learn to save resources and use them wise. Were getting Old :)

nc drill file to excellon ascii altium


What do you recommend for BGA via?
ordinary .6mm/.2mm via with 6mil clearance punch whole plane under the BGA device. It make impossible to access to the inner pins of device!

altium thermal pad

I can't give you a via size without knowing the BGA pitch, and the manufacturing limits of your fab.

There is no standard via size. Your fab will tell you what minimum hole and annulus they can manufacture. You then adjust your via size, hole size, and plane clearance according to the BGA pitch, and the manufacturing limits of your fab house.

If you are using true planes, and not poured polygons, the clearance that you set for the plane clearance is the clearance from the via hole and not from the pad annulus size. You adjust the design rule for the plane clearance to give you at least the minimum width of copper on the plane that your fab says it can handle.


    Points: 2
    Helpful Answer Positive Rating
plated pad without solder mask altium

Agree with Frosty, AD is way backward. Though I hv AD installed, I still prefer the old 99SE instead - believe me, its a breeze to use (if you know what you're doing...)

Added after 15 minutes:

For more complex board (esp. involving multilayer & HDI) I use MG2004 which is more powerful than AD.
Yes it is more difficult to use, esp. during library creation, but once you sort that out you're on top gear! (Got to see it when you do track push & shove or component drag..)
Try not to use smaller than 3mils via holes since not many Fabs able to do them.
Of course you hv to resort to blind or buried vias method for smaller pitched BGA packages such as uBGA.

altium find unique id

The device is 1148 bga, 1mm pitch.

Are you recommending special via? We always use an ordinary via which has the same spec in middle layers and top and bottom layer!

AD in nano-board reference designs has via which dirrectly connected to planes! Is this acceptable for pcb manufacturer? Or we have to use thermal connection?

pads binary translator

There are manufacturer's application notes that give recommended via sizes to fanout 1mm pitch BGAs. I suggest you take a look at for an example. Page two gives PCB layout recommendations.

Yes, you can use direct connections to the plane for BGA fanout vias. Thermal vias or pads are only necessary when you are soldering directly to the via or pad annulus. The purpose of a thermal is to increase the thermal resistance of the pad or via so the plane connection doesn't absorb all of the heat while you are trying to solder. In the case of a fanout via, the short stub of track between the BGA pad and the via serves the same purpose as a thermal connection would on the plane - therefore, you can make your via connection directly to the plane.


    Points: 2
    Helpful Answer Positive Rating
altium via rule tenting

1-Between PADS and Allegro, which one do you prefer?
2-Is drill info embedded to gerber files, or it must be generated separately?

altium re-annotation

PADS is easier to use, cheaper than Allegro, and will run on older, slower, computers. Allegro has more advanced signal analysis tools. It depends on your design needs and wealth, which one would be the best choice.

There are NO translators to or from the Allegro .BRD file format if you decide in the future you need to move the design to a different EDA platform. Once you design a board in Allegro, you're stuck in Allegro. There are PADS file translators available in several EDA packages, including Altium Designer.

Drill information must be generated separately. There are two Gerber formats, RS-274 and RS-274X. RS-274X embeds the aperture table into the Gerber file, RS-274 requires that you provide a separate aperture table. Both formats are only the shapes and lines on the board - the drill data must be provided separately. Excellon is the preferred format for the drill file.


    Points: 2
    Helpful Answer Positive Rating
generating excellon drill file in ascii altium

It seems that you perefer PADS to Allegro!?
In AD menus: file->fabrication outputs, three comands exist for drill info:
1) Composite Drill Guide
2) Drill Drawing
3) NC Drill File
which one is able to generate Excellon drill data? what is difference between them?
Also my FAB ask about layer order, I was wondering that gerber file extension contains this info! what do you suggest?

camtastic gerber buried vias

I prefer Altium Designer over PADS, and PADS over Allegro for ease of use laying out boards that do not require a great deal of signal integrity analysis. For complex boards requiring detailed signal integrity analysis, Allegro is superior. Allegro is much more difficult to use than either Altium or PADS. PADS is more difficult to use than Altium.

A "composite drill guide" is a drawing that shows where each hole in the board is drilled.

A "drill drawing" is the drawing where you place your instructions to the fab for the board. It also shows the hole placement and sizes using symbols. If you place a special text string called ".Legend" on the drill drawing, Altium makes a table of drill sizes and drill counts for you.

The NC drill file produces the actual drill files. In Altium, there are two types of drill files produced. One is binary which is seldom used by any fabrication shop these days, and the other is a .TXT file. The .TXT file is the Excellon drill file in ASCII format - this is the one that your fab will want.

You define the layer order. It isn't automatically determined for you by the software. Usually, you would make a table on the drill drawing that shows your desired stackup (layer order). In Altium Designer, there is a Layer Stack Manager under the "Design" menu. That stack manager allows you to define your layer order, layer spacing, materials, etc. Under the "Tools" menu, there is a function called "Layer Stackup Legend" that lets you place a graphical representation of the stackup on one of the mechanical layers (you would normally use the drill drawing). You select what you want in the stackup legend by hitting the "tab" key after you've placed the first corner of the legend.


    Points: 2
    Helpful Answer Positive Rating
1148 bga

Dear House_Cat:

It seems that gerber is not enough for PCB MFG and we must include more info on some layers and also generate other info!

Let us review the process from begining, suppose that we have finished the PCB design without any DRC and SI errors in AD, and ready for mask generation:

1) What information must be added to what specific layer?

2) which files must be generated? which Gerber layers? we were omitting mechanical layer! which seems to be bad idea!!!

3) What instruction are needed by fab in order to be able to finish a multi-layer board? layer stack-up, material, and ...?

4) Do I need to specify what gerber file are related to which layer, or file ext is enough?

5) AD6.7 generate .cam file, but fab do not recognize it! what is the matter?

6) Origin in AD is set to bottom left corner of design sheet, is it acceptable for mask and drill information generation? or we have to set the origin to other place? if so, where is suitable: left-bottom corner of baord or center of it?

7 ) How we can check the mask and pad overlapping? This check is not included in ordiniary DRC rules of AD! My fab was talking about IPC standard regarding this issue, what is this standard?

8 ) Can we apply via tenting on gerber mask using Camtastic or it must be done in original design files?

Thanks again,

Not open for further replies.

Part and Inventory Search

Welcome to