Problem with a "while loop" in the hdl coder

[marinet]

Hello,

I have written a matlab code and I try to produce a vhdl code by using the hdl coder. The problem is that the following error is appearing during the procedure of the code generation. "Found an unsupported unbounded loop structure. This loop may be user written or automatically generated due to the use of specific vector expressions or functions. For more information on unsupported loop structures, please refer to the documentation."

I have in the code a "while loop" and it seems that this is the error. My while loop has the following form:

while(A(i,j)>=0)
DD(i,j)=DD(i,j)+1;
A(i,j)=A(i,j)-7;
end

where A is an array and takes value from a subtraction: A(i,j)=abs(parti(i,j))-7;


Does anyone know why this error appears? As I know, the vhdl supports the "while loop".

 

[permute]

Support for some features of VHDL are for simulation only. I'm not familiar with hdl coder, so it might not be able to do anything suitable with the while loop to make it synthesizable.

 

[FvM]

Usuallly while loops aren't supported for synthesizable VHDL. This is specified in IEEE 1076.6-2004 (RTL synthesis) and also applies to tools not strictly following this standard.

Technically, only loops with "bounded" iteration number can be synthesized, because they are enrolled to parallel logic. The shown snippet seems completely unsuitable for synthesis. As far as I know, the Matlab HDL coder is targetting to synthesis, so this looks either like a bug or wrong configuration of the tool.

 

[TrickyDicky]

As fvm said, hdl coder is pretty black and white when it comes to what will and will not convert. So the only answer is replace the while loop.