Dear all, I am an intermediate-level verilog programmer. I was out of touch with Verilg programming so not really sure whats wrong with the following piece of verilog code.
Code:
module single_bit(
input [1:0] a,
input index,
output out);
reg out;
always @ index
out = a[index];
endmodule
and the test bench:
Code:
module test_single_bit;
reg [1:0] a;
reg index;
wire out;
single_bit uut (
.a(a),
.out(out),
.index(index));
initial begin
#100
a = 2'b01;
index = 1'b0;
#100;
index = 1'b1;
end
endmodule
when I simulate it using xilinx ISE 13.1,
a remains 'zz' for all the time
index remains 'z' for all the time
out remains 'x' for all the time
Variables do no change their value even once. What could be the possible problem?
you assign input values after 100 time units, if by chance the default
simulation time is the same or shorter you will get the results described;
change: initial begin
#100
a = 2'b01;
index = 1'b0;
to initial begin
a = 2'b01;
index = 1'b0;
---
have fun
you assign input values after 100 time units, if by chance the default
simulation time is the same or shorter you will get the results described;
change: initial begin
#100
a = 2'b01;
index = 1'b0;
to initial begin
a = 2'b01;
index = 1'b0;
---
have fun
module test_single_bit;
reg [1:0] a;
reg index;
wire out;
single_bit uut (
.a(a),
.out(out),
.index(index));
initial begin
#100
a = 2'b01;
index = 1'b0;
#100
index = 1'b1;
end
endmodule
Remove the semicolon, you will see expected results in ISIM
I dont know whats wrong. I have previously used modelsim. Are there any simulation/project settings specific to ISIM, which might be causing problems for me?