Binome
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Hi,
here's how I write a register in VHDL:
And I simulate it with modelsim. When forcing d to 1 or 0, it's ok, q is the same one clock cycle later. But when letting modelsim forcing d as a clock signal (period is 4 times the period of clk) then q is equal to d without the one-cycle delay.
Why?
here's how I write a register in VHDL:
Code:
process(clk,rst,d)
begin
if (rst = '1') then
q <= '0';
elsif (rising_edge(clk)) then
q <= d;
end if;
end process;
Why?