Problem when simulating a register

[Binome]

Hi,
here's how I write a register in VHDL:

	process(clk,rst,d)
	begin
		if (rst = '1') then
			q <= '0';
		elsif (rising_edge(clk)) then
			q <= d;
		end if;
	end process;

And I simulate it with modelsim. When forcing d to 1 or 0, it's ok, q is the same one clock cycle later. But when letting modelsim forcing d as a clock signal (period is 4 times the period of clk) then q is equal to d without the one-cycle delay.
Why?

 

[axcdd]

Hi,
first u can remove d from sensivity list as process is not sensitive to it.
when u force d as clock signal then in simulation d changes the same delta time as your clock -> so on the rising edge of clk d is assigned a new value that is transfered in clk process. (there is no setup and hold time in simulations).

You can emulate d changes in a simple process:

process(CLK)
begin
if rising_edge(CLK) then
d <= not d;
end if;
end process;

as all CLK sensitive processes run in the same time, d will get new value in current system time +1 delta, so q will store d's older value as its executed in 0 delta .

 

[TrickyDicky]

you really need to post the testbench code for us to analyse it. Using signal forcing is not really recommended testing approach, as it may cause the prioblems axcdd describes.

 

[kaiserschmarren87]

Hi,
here's how I write a register in VHDL:

	process(clk,rst,d)
	begin
		if (rst = '1') then
			q <= '0';
		elsif (rising_edge(clk)) then
			q <= d;
		end if;
	end process;

And I simulate it with modelsim. When forcing d to 1 or 0, it's ok, q is the same one clock cycle later. But when letting modelsim forcing d as a clock signal (period is 4 times the period of clk) then q is equal to d without the one-cycle delay.
Why?

process(clk,rst)
	begin
		if (rst = '0') then
		  if (rising_edge(clk)) then
			q <= d;
		end if;
	end process;

 

[TrickyDicky]

Was there any meaning to your incorrect code?

 

[K-J]

And I simulate it with modelsim. When forcing d to 1 or 0, it's ok, q is the same one clock cycle later. But when letting modelsim forcing d as a clock signal (period is 4 times the period of clk) then q is equal to d without the one-cycle delay.
Why?

Because you changed 'd' and 'clk' at exactly the same time. Leave 'd' the way you have it, but have 'clk' skewed over by a couple of nanoseconds.

Kevin Jennings

 

[Binome]

It's ok. I've corrected it and the simulation is good.
What I don't know is the behavior after synthesis. How to be sure d will be delayed?

 

[ads-ee]

What I'd like to know is do you really want to hold the q value when rst is high? Its certainly not resetting q the way you wrote it.

Regards

 

[Binome]

No, ok I wrote it too quickly. In fact I don't need a rst signal.

But tell me why it's not resetting q.

 

[ads-ee]

Opps,

Sorry my mistake...reading the forum on a phone doesn't work so well...when code is within syntax tags it doesn't show up when using the default mobile style!\

saw this code an thought it was your code.

process(clk,rst)
begin
	if (rst = '0') then
	  if (rising_edge(clk)) then
		q <= d;
	end if;
end process;

This code doesn't reset q and rst is an asynchronous active low enable.

Not sure who takes credit for this poorly written register template, but I wouldn't use this in any design that I wanted to work.


Regards

 

[LotusElectronics]

The Simulation Loop phase has two subphases: the Loop Initialization phase and the Loop Iteration phase. The initialization phase occurs once, at the start of the loop. The iteration phase is repeated once per time step from the simulation start time to the simulation stop time.

At the start of the simulation, the model specifies the initial states and outputs of the system to be simulated. At each step, new values for the system's inputs, states, and outputs are computed, and the model is updated to reflect the computed values. At the end of the simulation, the model reflects the final values of the system's inputs, states, and outputs. The Simulink software provides data display and logging blocks. You can display and/or log intermediate results by including these blocks in your model.

 

[TrickyDicky]

The Simulation Loop phase has two subphases: the Loop Initialization phase and the Loop Iteration phase. The initialization phase occurs once, at the start of the loop. The iteration phase is repeated once per time step from the simulation start time to the simulation stop time.

At the start of the simulation, the model specifies the initial states and outputs of the system to be simulated. At each step, new values for the system's inputs, states, and outputs are computed, and the model is updated to reflect the computed values. At the end of the simulation, the model reflects the final values of the system's inputs, states, and outputs. The Simulink software provides data display and logging blocks. You can display and/or log intermediate results by including these blocks in your model.

Why are you talking about simulink?