`define CALC_SWITCH 2
module MemIPTest(
DA,
DB,
error,
max_clk,
clk
);
// Interface variables
output reg [15:0] DA;
output reg [15:0] DB;
output reg error;
output max_clk;
input clk;
// Internal variables
reg[23:0] counter = 0;
reg[11:0] lindex = 0;
reg[11:0] rindex;
reg signed[17:0] da;
reg signed[17:0] db;
reg pll_lock;
reg spi_clk;
// Realtime
// Generate clocks
SysClkPLL system_pll(
.inclk0(clk),
.c0(sys_clk), // Changed sysclock out sys clock
.c1(max_clk),
.c2(spi_clk),
.locked(pll_lock)
);
// Get data from memory
sig_rom signal(
.address_a(lindex),
.address_b(rindex),
.clock(sys_clk),
.q_a(da),
.q_b(db)
);
always@(posedge clk) begin
if(max_clk == 1) begin
counter <= counter+23'h000100; // Add 2^8, therefore counter[23:8] will count 1 by 1 from 0 to 2^16 - 1
if(counter < 23'h001000) begin // Generato output sync pulse for oscilloscope
error <= 1;
end
else begin
error <= 0;
end
// Calculate lindex and rindex for addressig the dual ROM
lindex <= counter[23:12]; // Get a 12 bit addressing value from array
rindex <= lindex + 1024; // Calculate cosine value from 1/4 phase
end
else begin
case(`CALC_SWITCH)
0:
begin
// Check the counter value (works fine on the oscilloscope, observed exactly as it should be).
DA <= counter[23:8]; // Get a 16 bit value for output from counter
DB <= counter[23:8]; // Same on channel B
end
1:
begin
// Check the index values on the oscilloscope. Works fine, values are as expected.
DA <= lindex << 4; // Restore a 16 bit value for observation on the scope
DB <= rindex << 4;
end
2:
begin
// Check the values of the ROM. Does not work. The da and db values are apparently not generated from sig_rom
// I get only 0s.
DA <= da[17:2]; // Make a 16 bit value from 18 bit.
DB <= db[17:2];
end
endcase
end
end
endmodule
module sig_rom (
address_a,
address_b,
clock,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] sub_wire2 = 18'h0;
wire sub_wire3 = 1'h0;
wire [17:0] q_a = sub_wire0[17:0];
wire [17:0] q_b = sub_wire1[17:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire2),
.data_b (sub_wire2),
.wren_a (sub_wire3),
.wren_b (sub_wire3),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
`ifdef NO_PLI
altsyncram_component.init_file = "sine18_4k.rif"
`else
altsyncram_component.init_file = "sine18_4k.hex"
`endif
,
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
If a ROM can't be inferred as intended, the compiler warnings will show you why. With MAX10, you need to select a configuration scheme with memory initilization, otherwise no ROM and initialized RAM is possible.
I'm not sure what it means, but I'm working with the lite version, without a license
Thanks
Error (176029): Memory block signal_maker:comb_3|dual_port_rom:sine|altsyncram:rom_rtl_0|altsyncram_f071:auto_generated|ram_block1a8 uses a global signal on its clock-enable1 port. This is not allowed for this family.
Altera® FPGAs and Programmable Devices
FPGA or field programmable gate array is a semiconductor integrated circuit where electrical functionality is customized to accelerate key workloads.www.intel.com
sys_clk_pll sys_clocks(
.areset(0),
.inclk0(clk),
.c0(sys_clk),
.c1(max_clk),
.c2(spi_tempo),
.locked()
);
dual_port_rom sine(
.ldata(datal),
.rdata(datar),
.laddr(addl),
.raddr(addr),
.clk(sys_clk),
);
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?