problem simulation delay line

[yefj]

Hello , i was given a schematics which is supposed to be pulse delay .
my pulse is 3.3V and 220nS wide, but instead of a pulse on the outside i get a huge overshoot .
I know that LC system is a differencial equation which can lead to overshoot but its supposed to be a pulse delay.
Where did i go wrong?
LTspice file is attached.
Thanks.

 

[yefj]

Hello Tony,you succseeded to do a huge delay in the line below. i tried to create a 3section network also, but i get only 12nS shift.
what is the mathematical logic behind such a large delay?

 

[D.A.(Tony)Stewart]

What did you change? i.e. Don't change anything unless you understand the consequences or how it works..

 

[yefj]

Hello Tony, smaller pulse width ,smaller L smaller C.
How this works mathematickly?
Thanks.

 

[D.A.(Tony)Stewart]

Elementary if you are a graduate. I assumed you were. Was I wrong?

ωo = 1/√(LC)

τd = √(LC) = 1/ ωo and maximally flat τd up to ωo using Bessel low Q filters.

So high BW causes low Tau. Doesn't that make sense.

Other filters have higher Q such as Butterworth (0.707) and more with Chebychev which have steep peak group delays at the poles near cutoff due to higher Q, yet your spectrum is weak there as it sets up the steeper cutoff. The lowest Cheby. PB ripple =0 dB filter then it becomes a Butterworth. This ghroup delay distortion also cause jitter in data pulses from distortion in eye patterns, so Gaussian or Raised Cosine or similar are used for continuous synchronous data pulses for low ISI (InterSymbol Interference.) Yet here you only assume 1 pulse.

 

[yefj]

HelloTony, by the expression tau=69.5ns=0.069us so i need to multiply it by 3 in order to get the delay of the whole network?
correct?
Thanks.

--- Updated Apr 8, 2024 ---

UPDATE:
Hello Tony, If we build the sytem without the diode structure and i see a very big amplitue.
What is the logic of the structure you built to make the output resemble more of a pulse like shape.
Is there a name for such circuit?
Thanks.

 

[D.A.(Tony)Stewart]

HelloTony, by the expression tau=69.5ns=0.069us so i need to multiply it by 3 in order to get the delay of the whole network?
correct?
Thanks.
View attachment 189917View attachment 189916

--- Updated Apr 8, 2024 ---

UPDATE:
Hello Tony, If we build the sytem without the diode structure and i see a very big amplitue.
What is the logic of the structure you built to make the output resemble more of a pulse like shape.
Is there a name for such circuit?
Thanks.
View attachment 189918

You assumed BW from LC which is just for one stage or a 2nd order filter.
Cascaded filters are more complex in computation and might be done using matrices.
Can you see the difference cascading faster filters makes?
Lumped equivalent circuits for coax are infinite for 0 error, but sometimes 20th order delay lines are created.
For Audio, they just use a mechanical spring or a hallway.

We used to use 50 x 2 ns delay lines to measure data "Window Margin" to measure clocking errors by shifting early or late relative to PLL clock to measure bitshift with 2% resolution on 10MBaud datastreams in the 80's from the 1st 5.25 " HDD's to map disk defects, asymmetry, group delay distortion and timing defects.

Analog Oscilloscopes use delay lines to capture the signal with an early trigger so the delayed signal can be displayed.

But you seem to have unusual requirements for no purpose when you could use a digital clocked delay, if it is a synchronous pulse.

>(Diodes) Is there a name for such circuit?
How much electronics did you study?

It's a simple R-D "diode clamp that attenuates like a R-divider from the threshold voltage using V/I curve slope at If or the incremental resistance which limits to the fixed bulk resistance dependant on Rb~ 1/Pmax (est. +/-50%)

So ESD protection in CMOS once used 2 stages for 1 to 5 kV impulses to attenuate to 200 mV with high ESR low pF fast diodes. Now they used more complex active devices to clamp ESD in all CMOS logic with limits on energy.

 

[BradtheRad]

You're on the right track with your conjecture about LC time constant. I have run a variety of this kind of simulation. If all stages have identical LC values, then each stage adds the identical length of phase change.

Here are values demonstrating that ringing resonance starts at the first LC stage. Initial current charges the first C, which regurgitates the charge immediately back up to the inductors. The same process (governed by the LC time constant, looks like 0.7 mSec per stage) propagates a bit more delay with each LC stage.

 

[D.A.(Tony)Stewart]

You're on the right track with your conjecture about LC time constant. I have run a variety of this kind of simulation. If all stages have identical LC values, then each stage adds the identical length of phase change.

Here are values demonstrating that ringing resonance starts at the first LC stage. Initial current charges the first C, which regurgitates the charge immediately back up to the inductors. The same process (governed by the LC time constant, looks like 0.7 mSec per stage) propagates a bit more delay with each LC stage.

View attachment 189919

For 16th order Ladder filter with 8* 0.7 ms/stage = 5.6 ms delay, slightly more than 1/f but with significant attenuation using 10% of 200 Hz or a half pulse at 4kHz with a sqrt(LC) *Q = 1ms seems like 0.707 factor for a Ladder Filter per LC stage..

hmm Any Math experts on Filters here?

Wikiwand - Group delay and phase delay

In signal processing, group delay and phase delay are two related ways of describing how a signal's frequency components are delayed in time when passing through a linear time-invariant (LTI) system. Phase delay describes the time shift of a sinusoidal component. Group delay describes the time...

www.wikiwand.com

I was wrong before in stating Group Delay from LC alone for breakpoint fo with frequency = 0 but with Q the impedance ratio for each stage. (?)

does not look right.

is the group delay near DC of f=0

 

[yefj]

Hello,I am trying to build a single cell of delay as shown below , by the calculation i am supposed to get a 70ns=0.07usec delay between the pulses.
However when i zoom into the plot i dont see any move between them just a different rise time.
Why i cant see the 70ns shift between pulses?
Thanks.

 

[FvM]

Look sharp. The capacitor in your circuit is shorted by the voltage source and has no effect at all. You're simulating a first order RL filter, the formula doesn't apply.

 

[D.A.(Tony)Stewart]

It also looks like an error in assumptions or setup to not get an exponential ramp.