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problem regarding internal power of Dflip flop.

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ramaswami

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about internal power

hi every one
I have a problem regarding internal power of Dflip flop. Actually i designed a FIFO, in
that i used registers. I extracted power (using PRIME POWER )of that FIFO by giving different switching activities of the input pins of the FIFO. Most of the power is consumed by registers.
Even for switching activity 0.9 , the power is dominated by internal power of the registers.
i have seen nearly 90% of the power is consumed by internal of the registers.

PRIME POWER inputs that i have given
period - 1000000(1 msec)
clk period - 5ns
toggles - ___
probability of 1 - _____

LIBRARY information -- FARADAY 90nm

last two inputs are given based on the SYSTEM C simulation outputs of the FIFO. plz tell me what is the internal node in DFlipflop. i have seen in library the internal power is specified for clk. can any one tell me what is the schematic of DFlip flop. plz help me...

thank q
 

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