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Problem on Load Regulation of LDO?

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Oct 9, 2005
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load regulation in ldo

Hi all,
I have designed a LDO. But the load regulation of it didn't seem good.
(1) when the load current jumps from heavy to light, the output voltage have a 3.6V(the battery voltage) spark.
(2) And when the load current jumps to heavy, the output voltage has a very low voltage spark (about 0.6V).
You can see the simulation waveform in the attachment.
I think the spark is too large. What is wrong with it? And how can I deal with this problem?

BTW: the output capacitance is 4.7uF.


when i do sim of heai load ldo , i meet the same problem ,may be you output driver vol is not enough to cut off your output driver when the ldo is at the light load condition ! the other reason may be your driver size is very large and the Ron is very large ,so when the driver is at the light load condition the leakage current is large ! you can check the output vol of the pre-stage before the output

Maybe because the settling time of the feedback loop is long, and when the load suddenly change, there is a big voltage change appeared at the gate of power MOSFET and induce a voltage spike through the paracitic capacitance Cgd. If i am wrong , please point out . Thanks.

maybe your power mos is not so large.

yeah, maybe the gm of the power mos is not enough, so when there is large current change occur at the output node, the power mos can not absorb the current change quickly enough.

Thank you very much!
I have changed the pass mos for a big one, but there has a little improvement.
My pass mos's size is 15 by 100u/0.4u 10 fingers in 0.18 process. Is it too small to pass 300mA current?

I've ever designed audio power amplifier, and in order to drive about 500-600mA current in the saturation region, the output PMOS size is 400*(90/0.6). So i guess your power mos is too small.
Also, suggest you check the OP amp's characteristics, such as gain, bandwidth, and so on.
Hope it help.

I have replaced the op for those with different characteristics, but the problem is still over there.
I guessed it maybe because of the model of the output capacitor.
The output capacitor I used is the cap cell in the analogLib.
I am puzzled. who can help me?
: )

mu......did u try just using a simple, ideal cap ? if u got the right result, at least prove the problem is from the cap u using.

by the way, why don't u use smallest channel length ? i heard this is better for the Vo ....

and, plz to upload yr schematic share with us

Some points.

Somebody said something about your pass transistor. If Mpass gets bigger, the Ron decrease. It is simply because the current is going to have more path to pass through. So, your Mpass was very small and still is, specially for your 300mA output. It should be a very tough system to source If you need to supply that amount of current.

About the output capacitor, you don't post anything about stability issues. Which ESR has your Cout ? You need that in order to generate the zero needed to gain a little bit of phase margin.

Also you have to fight against the slewing. If your primary target is the transient response, you should increase your Iq so you won't take too long to charge the parasitic capacitance of Mpass. How big is your actual Iq (Ignd) ???

Please double check:
1.decrease the ESR of the out;
2.increase the GBW of the LDO;
3.increase the Cout

Cap from analoglib should be ok and correct in your simulation.
Maybe the stage to drive the Pass transistor is too weak. That is, its current is too small.

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