Problem of LNA design input port

[whitewiz]

I am doing the 100 MHz LNA design.

It is really curious that I can not get the ouput at all if I put the Coupling Capacitor

(10 pF) series with the gate of the transistor. Usually, we can put the coupling cap

in the input side to avoid the parasitic signal.

The input setup is wrong ??

 

[gszczesz]

Post your circuit here...

Without looking at your circuit, I'm guessing that when you put the coupling capacitor in, you do not properly bias the gate of the transistor because you're blocking your DC.

Greg

 

[whitewiz]

Post your circuit here...

Without looking at your circuit, I'm guessing that when you put the coupling capacitor in, you do not properly bias the gate of the transistor because you're blocking your DC.

Greg

 

[gszczesz]

When you specify 350mV DC voltage on the port, it generates 700mV internally, and then puts the 300 Ohm resistor in series. I'm guessing that the NMOS reference you are using does not give you 750mV but something else....

What is the DC current, and more importantly DC voltage on the gate for both cases?

Greg

 

[bcl]

Have you tried a larger value coupling cap? You might be cutting off the 100MHz input with the high pass structure?