Problem of LDO design

[twteng]

Hi all:
I am designing a LDO as show in attached, Can anybody tell me how to decide the Vx? my spec. of vin range is 2V~5V
regulated output voltage is 1.8V.
Usually, we'll design Vx to vdd/2, but that will enlarge the size of power mos, and induced more parasitic capacitor in the node of Vx,
Can I design the Vx slightly less than vdd/2 to reduce the size of power mos? Does it has any side effect?
Moreover, Does the error amplifier need buffer to drive power mos??
I am glad to hear any suggestions, thanks.

Eason

 

[erikl]

First, your schematic shows positive feedback: both your Error Amplifier and Pass Transistor are inverting. Exchange the inputs of the Error Amplifier!

Can I design the Vx slightly less than vdd/2 to reduce the size of power mos?

After having done the a.m. exchange, this is a regulation system. Vx will be adjusted correctly, independently of transistor size.

Does it has any side effect?

Yes: as smaller the size as lower the headroom, i.e. higher dropout voltage (Vds of Pass Transistor).

Moreover, Does the error amplifier need buffer to drive power mos??

Depends on your speed requirements: the error amplifier should deliver enough current to charge the gate input capacitance fast enough for your regulation accuracy.

 

[twteng]

Thanks erikl's reply, that really helpful.
I have another query, what operation region should power-mos be operate?
linear or sat.?
look forward your opinion, thank you.

 

[erikl]

what operation region should power-mos be operate? linear or sat.?

For good regulation the power-mos should operate in saturation region. Operation in linear region (Vds < Vdsat) means small gain, bad regulation, operation in dropout condition.