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problem of charge pump

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zhenywu

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cadence plllib bandwidth gain

I have a puzzle when I design a PLL. How do I design the currents of charge pump? Can we use formulas to calculate them or just estimate them?



THANKS
 

yeechyan

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You need to know the kn and kp of the transistors. From the kn and kp, calculate the W and L for your transistors according to the currents required for the charge pump.
 

zhenywu

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yeechyan said:
You need to know the kn and kp of the transistors. From the kn and kp, calculate the W and L for your transistors according to the currents required for the charge pump.
Thank you, but I mean how to decide the currents required for the charge pump.
 

Japp

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Well this partly depends on what loop gain you want. The larger current you use the larger capacitors needed for the loop filter. So if you intend to integrate the loop filter on the chip go for small currents. But often larger currents are better for suppressing noise and spurs (well the larger noise can be a sideeffect of to large resistors in the loop filter combined with a high kvco!).
You can get a good idea of the possibilities by playing with the variables in the free program ADIsimpll (from analog devices). Here you can also control the individual noise contributions, the bandwith etc.
You can find some of the formulas (if you insist) in Deans Book (go Google).
 

eng_Semi

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Ip is considered from the system level design of the PLL, so u must first put the required specs (settling time, spurs, phase noise, .. ) and then try an initial value for the CP current, then simulate. If this current met the specs, so its OK. If not try to change it and simulate again.

U may use MATLAB for the system level design
 

uncle_urfi

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ωn=squareroot {(1/N)*(Kvco*Ip)/(2*pi*C2)}

Hence quadrupling the CP current will double the loop bandwidth. If C2 (the main capacitor) is outside the chip, it can be large, and you need an Ip that is large.

If the C2 is on chip, then the max value is about 1nF. and that will determine the Ip.
The discussion assumes that Kvco is uniform over the CP voltage range.
Try Eagleware's =PLL= program or use the pllLib in Cadence to simulate your PLL.
 

mmohsen

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Hi


try to download [ PLL Basics-Loop filter Design ] for Fujitsu Microelectronics, Inc.
i think it will help you when trying to held your system ,
and i think that you should keep in mind that the design issue is in usual full of trade-off's so try first to find your Specs and start optimizing your desgin for your application. eg; (spur level, noise and settling time which is dependent on the Loop filter BW and Ip ,Ko ... ) they are all related to each other
so i think that this paper will help you to ramp up in the system-level design try to follow it , if u didnot find it tell me and i will upload it to you , and try to write a Matlab code it will help u to speed up your design time.

best regards

Mohamed Mohsen
 

khouly

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dear mohamed mohsen

upload it

thanks

khouly
 

mmohsen

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here is the paper
 

layes2

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if i use cap=100p
i would begin with icp =20ua
 

jotamario

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You must start knowing that the fc of your loop must be less than 1/10 the reference frequency. Then there is a relation between this fc of your loop and the wn of your loop (it is not the same, the last is the wn obtained in the denominator of your laplace function). With wn use the formula given for uncle_urfi to obtain Ip.
 

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