no.Do you have the testbench..?
in that case output always assigned to 0.You must define initial value for reg output 'o' .
For example,
initial o=3'h0;
Output is not initialized to any value.
So it will take XX only.
If you perform any operation with X's you will get x only.
If it is synthesizable code
use one pin to reset the value of registers
else
you can use initial(it will execute only once not always) or the way you have initialized the variable count.
can u post your test bench here
You must define initial value for reg output 'o' .
For example,
initial o=3'h0;
Post please the vectors you send to the module, i.e. i = 8'h....(or maybe you can attach waveforms) If the lsb of the vectors is 1 then you will always get count=0 ( your code do that: see the portion of the code where else statements take place).
Are you going to synthesize this code?
This code is not synthesizable. Elaborate your design please (synchronous logic or pure combinational logic; function).
You're sending to the module 8'hA4 = 8'h10101000... Let's follow your code.
Enter to always@ block...
Initial values for count and o is 0...
1 iteration of for cycle:
i[7]==1 -> o = count = 0;
count = 0;
2 iteration of for cycle:
i[6]==0 -> count = count + 1 = 1;
o = old_value = 0;
3 iteration of for cycle:
i[5]==1 -> o = count = 0;
count = 0;
4 iteration of for cycle:
i[4]==0 -> count = count + 1 = 1;
o = old_value = 0;
3 iteration of for cycle:
i[3]==1 -> o = count = 1;
count = 0;
2 iteration of for cycle:
i[2]==0 -> count = count + 1 = 1;
o = old_value = 0;
1 iteration of for cycle:
i[1]==0 -> count = count + 1 = 2;
o = old_value = 0;
0 iteration of for cycle:
i[0]==0 -> count = count + 1 = 3;
o = old_value = 0;
So the answer is 0..
----------
Good luck!
Yes, sorry.... The final value is 2... Fix condition for the for loop, i.e for(j=7;j>=0;j=j-1). I've modeled the code and as expected it returns 2 for 8'hA4.
But it's still non-synthesizable code... Do not use for loop in a software manner, think about hardware (comb logic, flip-flops, etc) when you write HDL descriptions.
if(i[j]==0)
begin
count=count+1;
end
else
begin
o=count;
count=0; --- remove or comment this part and check. you are assigning count value zero here. It is under for loop. so it is causing the issue
end
end
end
endmodule
Then put outside the "for loop".
In FOR LOOP output will be updated after one complete run.
You cant see the intermediate results.
Since you are assigning the counter value to zero, it overrides the original value.
Even if you initialize the "o" as 1 also, it will give result as zero only
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