problem in verilog code with inout datatype

[arishsu]

Hi
there occured a problem with inout datatype declaration. The error says

"ERROR:HDLCompilers:247 - "IO_port.v" line 37 Reference to vector wire 'data_io' is not a legal reg or variable lvalue"

The code is as below

module IO_port(IOAR,in,out,IOW,IOR,device_addr,data_io,clk,data_acc
);
input in,out,IOR,IOW,clk;
input [7:0]IOAR;
inout wire[15:0]data_io;
inout wire[15:0]data_acc;
//wire [15:0]data_io,data_acc;
wire in_out;
output reg[7:0] device_addr;
assign in_out=(in || out);
assign device_addr=(in_out)?IOAR:8'bz;
always@(posedge clk)
begin
if(IOR)
data_acc=data_io;
else if(IOW)
data_io=data_acc;
else if(IOR&&IOW)
$display("operation error. IOR and IOW both active");
end
endmodule

 

[FvM]

Values assigned in sequential code must be reg not wire. Furthermore you need to assign 'z' state to inout ports to be able to read it (during IOR active).

It's also impossible to query a value for 'z' state in synthesized Verilog.

 

[arishsu]

Hi FvM,
I didn't get 'assign z states to inout ports'. How we do it? Can you show a simple example? I tried with reg too but the same error displayed.