Problem in verilog code for timer

[arishsu]

Hi,
I tried to simulate a code for a timer and I got an error when I tried to synthesize on ISE. The error is as below.
"ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more."
"ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more."

my code is pasted below.


module timer_unit(LDTIM0,LDTIM1,LDTIM2,STRTIM0,STRTIM1,STRTIM2,clk,data,TIM0,TIM1,TIM2
);
input [15:0]data;
input clk,LDTIM0,LDTIM1,LDTIM2,STRTIM0,STRTIM1,STRTIM2;
output TIM0,TIM1,TIM2;
timer T0(LDTMR0,STRTIM0,clk,TIM0,data);
timer T1(LDTMR1,STRTIM1,clk,TIM1,data);
timer T2(LDTMR2,STRTIM2,clk,TIM2,data);
endmodule

module timer(LDTIM,STRTIM,clk,TIM,data);
input LDTIM,STRTIM,clk;
input [15:0] data;
output reg TIM;
reg [15:0]tmr_count;
initial tmr_count=16'b0;
always@(posedge clk)
begin
if (!LDTIM)
tmr_count=16'b0;
else
tmr_count=data;
/* end
always@(posedge clk)
begin
if (STRTIM)
begin*/
while((tmr_count>0)&&STRTIM)
begin
tmr_count=tmr_count-1;
end
while(tmr_count<=0)
begin
TIM=1;
end
end
//end
endmodule

 

[FvM]

You are misunderstanding the nature of iteration constructs in HDL. They are useless to implement a timer.

You'll have a reg variable tmr_count that's initially loaded and decremented each clock cycle (or initially zeroed, incremented and compared with end time) and some supplementing logic.

There are also violations of Verilog semantic, e.g. tmr_count is assigned in multiple always blocks.

 

[arishsu]

Hi FvM,
actually i used only one always loop. 2nd one is commented out.
So you are saying there is no possibility of making such a timer using verilog? Actually our professor gave this logic and asked me to write a code for that.
Any alternative solutions for this?

 

[FvM]

actually i used only one always loop. 2nd one is commented out.

Yes, I overlooked this.

I just realized, that you probably only have to write if instead of while to make the code work.