Problem in using Spectrum Function in Cadence IC6.13

amr.maghraby · Aug 1, 2019

i am using cadence IC 6.13 virtuoso to design an ADC

i am trying to measure the SNR of that ADC , so i build an ideal DAC using Veriloga and take the output of the ADC to the input of the DAC and then i took the output signal from the DAC and export it to the calculator of the Cadence and then i used the spectrum function to find snhr.

there is a relation that relates the sampling frequency , input frequency , no. of cycles , & number of samples in the output signal identified by murmann in his lectures fs/fin = no. of samples/ no. of cycles

the SNR of an ideal 9-bit ADC should be 6.02N+1.76 which will be ≈ 55dB , the problem is that the snhr is only 49 dB , can anyone help me why??

fs = 512MHz , cycles = 3 , no. of samples = 1048576 , fin = 1464.84375 Hz

sutapanaki · Aug 3, 2019

Maybe you should also do FFT and plot the spectrum. Thus you can see the harmonics and how large they are.
Also, do you wait enough time from the start of the simulations to let things settle initially?

BigBoss · Aug 3, 2019

I don't see any discrepancy here..
DAC is ideal by Verilog, the ADC is a circuit based right ??And you see 6dB difference in SNR compare to ideal one..
What is the problem ?? I think that is normal..

amr.maghraby · Aug 4, 2019

BigBoss said:
I don't see any discrepancy here..
DAC is ideal by Verilog, the ADC is a circuit based right ??And you see 6dB difference in SNR compare to ideal one..
What is the problem ?? I think that is normal..

no BigBoss
the ADC is also ideal with veriloga it should give me the ideal answer
and it did for the first 8-bits , but in the 9th bit through the 12th bit it gives me the same answer 49.4dB

pancho_hideboo · Aug 4, 2019

Show me netlist and ocean script.

amr.maghraby · Aug 4, 2019

pancho_hideboo said:
Show me netlist and ocean script.

the netlist

// Generated for: spectre
// Generated on: Aug 1 20:45:03 2019
// Design library name: ADC_Dynamic_Tests
// Design cell name: 9B_Ideal_ADC_nowindow
// Design view name: schematic
simulator lang=spectre
global 0
include "/root/tsmc13/tsmc13rf/../models/tsmc13rf.scs"

// Library name: ADC_Dynamic_Tests
// Cell name: 9B_Ideal_ADC_nowindow
// View name: schematic
I0 (net3 net4 net5 net6 net7 net8 net9 net10 net11 net12 net13 net14 net1 \
net2) ADC_12_bit trise=0 tfall=0 tdel=0 vlogic_high=5 vlogic_low=0 \
vtrans_clk=2.5 vref=5
I1 (net3 net4 net5 net6 net7 net8 net9 net10 net11 net049 net048 net047 \
Vout) DAC_12_bit vref=5 trise=0 tfall=0 tdel=0 vtrans=2.5
V0 (net1 0) vsource dc=2.5 type=sine sinedc=2.5 ampl=2.5 freq=1.46484375K
V1 (net2 0) vsource type=pulse val0=0 val1=5 period=976.5625p \
width=488.28125p
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/root/tsmc13/Comparator_Paper/ADC_12_bit/veriloga/veriloga.va"
ahdl_include "/root/tsmc13/Comparator_Paper/DAC_12_bit/veriloga/veriloga.va"

The ocean script

simulator( 'spectre )
design( "/root/simulation/9B_Ideal_ADC_nowindow/spectre/schematic/netlist/netlist")
resultsDir( "/root/simulation/9B_Ideal_ADC_nowindow/spectre/schematic" )
modelFile(
'("/root/tsmc13/tsmc13rf/../models/tsmc13rf.scs" "")
)
analysis('tran ?stop "2.052m" )
temp( 27 )
run()
selectResult( 'tran )
plot(getData("/Vout") )

pancho_hideboo · Aug 4, 2019

Why is there no Tran statement in netlist ?
On the other hand, ocean specify Tran with stop=2.052m.

Show me followings.

Verilog-A code of dac and adc.

Include spectrum function in ocean.
Then show it.
Or show me setting of spectrum function.

amr.maghraby · Aug 4, 2019

pancho_hideboo said:
Why is there no Tran statement in netlist ?
On the other hand, ocean specify Tran with stop=2.052m.

Show me followings.

Verilog-A code of dac and adc.

Include spectrum function in ocean.
Then show it.
Or show me setting of spectrum function.

the netlist

// Generated for: spectre
// Generated on: Aug 4 21:17:45 2019
// Design library name: ADC_Dynamic_Tests
// Design cell name: 9B_Ideal_ADC_nowindow
// Design view name: schematic
simulator lang=spectre
global 0
include "/root/tsmc13/tsmc13rf/../models/tsmc13rf.scs"

// Library name: ADC_Dynamic_Tests
// Cell name: 9B_Ideal_ADC_nowindow
// View name: schematic
I0 (net3 net4 net5 net6 net7 net8 net9 net10 net11 net12 net13 net14 net1 \
net2) ADC_12_bit trise=0 tfall=0 tdel=0 vlogic_high=5 vlogic_low=0 \
vtrans_clk=2.5 vref=5
I1 (net3 net4 net5 net6 net7 net8 net9 net10 net11 net049 net048 net047 \
Vout) DAC_12_bit vref=5 trise=0 tfall=0 tdel=0 vtrans=2.5
V0 (net1 0) vsource dc=2.5 type=sine sinedc=2.5 ampl=2.5 freq=1.46484375K
V1 (net2 0) vsource type=pulse val0=0 val1=5 period=1.953125n \
width=976.5625p
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=2.052m write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/root/tsmc13/Comparator_Paper/ADC_12_bit/veriloga/veriloga.va"
ahdl_include "/root/tsmc13/Comparator_Paper/DAC_12_bit/veriloga/veriloga.va"

the spectrum function settings are
no. of samples = 1048576
no. of noise bins = 0
start frequency = 0
end frequency = ـــــ default value
window type = blackman
ADC span = 0
measure type = snhr

ADC code

`include "discipline.h"
`include "constants.h"

// $Date: 1997/08/28 05:54:32 $
// $Revision: 1.1 $
//
//
// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996
//
//

//--------------------
// ADC_12_bit
//
// - Ideal 12 bit analog to digital converter
//
// vin: [V,A]
// vclk: [V,A]
// vd0..vd11: data output terminals [V,A]
//
// INSTANCE parameters
// tdel, trise, tfall = {usual}
// vlogic_high = [V]
// vlogic_low = [V]
// vtrans_clk = clk high to low transition voltage [V]
// vref = voltage that voltage is done with respect to [V]
//
// MODEL parameters
// {none}
//
// This model is ideal in the sense that there is no mismatch modeled.
//

module ADC_12_bit(vd11, vd10, vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vin, vclk);
electrical vd11, vd10, vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vin, vclk;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdel = 0 from [0:inf);
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 2.5;
parameter real vref = 5.0;

`define NUM_ADC_BITS 12
real unconverted;
real halfref;

real vd[0:`NUM_ADC_BITS-1];
integer i;

analog begin

@ ( initial_step ) begin
halfref = vref / 2;
end

@ (cross(V(vclk) - vtrans_clk, 1)) begin
unconverted = V(vin);
for (i = (`NUM_ADC_BITS-1); i >= 0 ; i = i - 1) begin
vd = 0;
if (unconverted > halfref) begin
vd = vlogic_high;
unconverted = unconverted - halfref;
end else begin
vd = vlogic_low;
end
unconverted = unconverted * 2;
end
end

//
// assign the outputs
//
V(vd11) <+ transition( vd[11], tdel, trise, tfall );
V(vd10) <+ transition( vd[10], tdel, trise, tfall );
V(vd9) <+ transition( vd[9], tdel, trise, tfall );
V(vd8) <+ transition( vd[8], tdel, trise, tfall );
V(vd7) <+ transition( vd[7], tdel, trise, tfall );
V(vd6) <+ transition( vd[6], tdel, trise, tfall );
V(vd5) <+ transition( vd[5], tdel, trise, tfall );
V(vd4) <+ transition( vd[4], tdel, trise, tfall );
V(vd3) <+ transition( vd[3], tdel, trise, tfall );
V(vd2) <+ transition( vd[2], tdel, trise, tfall );
V(vd1) <+ transition( vd[1], tdel, trise, tfall );
V(vd0) <+ transition( vd[0], tdel, trise, tfall );

`undef NUM_ADC_BITS
end
endmodule

DAC code

// VerilogA for Comparator_Paper, DAC_12_bit, veriloga

`include "discipline.h"
`include "constants.h"

// $Date: 1997/08/28 05:54:36 $
// $Revision: 1.1 $
//
//

//--------------------
// dac_12bit_ideal
//
// - 12 bit digital analog converter
//
// vd0..vd11: data inputs [V,A]
// vout: [V,A]
//
// INSTANCE parameters
// vref = reference voltage that conversion is with respect to [V]
// vtrans = transition voltage between logic high and low [V]
// tdel,trise,tfall = {usual}
//
// MODEL parameters
// {none}

module DAC_12_bit(vd11, vd10, vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vout);
electrical vd11, vd10, vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vout;
parameter real vref = 5 from [0:inf);
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdel = 0 from [0:inf);
parameter real vtrans = 2.5;

real out_scaled; // output scaled as fraction of 4096

analog begin
out_scaled = 0;
out_scaled = out_scaled + ((V(vd11) > vtrans) ? 2048 : 0);
out_scaled = out_scaled + ((V(vd10) > vtrans) ? 1024 : 0);
out_scaled = out_scaled + ((V(vd9) > vtrans) ? 512 : 0);
out_scaled = out_scaled + ((V(vd8) > vtrans) ? 256 : 0);
out_scaled = out_scaled + ((V(vd7) > vtrans) ? 128 : 0);
out_scaled = out_scaled + ((V(vd6) > vtrans) ? 64 : 0);
out_scaled = out_scaled + ((V(vd5) > vtrans) ? 32 : 0);
out_scaled = out_scaled + ((V(vd4) > vtrans) ? 16 : 0);
out_scaled = out_scaled + ((V(vd3) > vtrans) ? 8 : 0);
out_scaled = out_scaled + ((V(vd2) > vtrans) ? 4 : 0);
out_scaled = out_scaled + ((V(vd1) > vtrans) ? 2 : 0);
out_scaled = out_scaled + ((V(vd0) > vtrans) ? 1 : 0);
V(vout) <+ transition( vref*out_scaled/4096, tdel, trise, tfall );
end
endmodule

Click to expand...

pancho_hideboo · Aug 4, 2019

Show me all arguments of spectrum().
They are too few.

amr.maghraby · Aug 4, 2019

That is all the arguments in the spectrum function

pancho_hideboo · Aug 4, 2019

amr.maghraby said:
That is all the arguments in the spectrum function

Wrong.
You can not understand spectrum() at all.

Enter “ocnHelp ‘spectrum” in CIW.
Or launch skill finder and then enter “spectrum”

Problem in using Spectrum Function in Cadence IC6.13

amr.maghraby

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sutapanaki

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BigBoss

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amr.maghraby

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amr.maghraby

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