dipin
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hi,
i had designed a divider which perform -ve and +ve division . but i had a problem in this one. in this how can i represent -ve fraction .
in my design i am storing quotient to one register and fraction to another register so if the out put is -.5
( suppose 8 bit with 4 bit for fraction ) then 1111.1000
so it is exactly like -1.5.
so my doubt is how -1.125 , -.125 really represented in a fpga?
is it possible to take 2'complement of fraction(because it is 2^-1,2^-2...)??
what i do is if the result is negative then keeping the fraction as itself and taking the 2's complement of the quotient.
i dont have any idea what to do plz help me
thanks and regards
i had designed a divider which perform -ve and +ve division . but i had a problem in this one. in this how can i represent -ve fraction .
in my design i am storing quotient to one register and fraction to another register so if the out put is -.5
( suppose 8 bit with 4 bit for fraction ) then 1111.1000
so it is exactly like -1.5.
so my doubt is how -1.125 , -.125 really represented in a fpga?
is it possible to take 2'complement of fraction(because it is 2^-1,2^-2...)??
what i do is if the result is negative then keeping the fraction as itself and taking the 2's complement of the quotient.
i dont have any idea what to do plz help me
thanks and regards